CHAND NAGUBOINA, Gopi; ANUSUDHA, K.; SRAVYA, T. Realization and Synthesis of 4 - bit Universal Shift Register using Logical Reversible Computation in Xilinx. International Journal of Engineering and Technology, [S. l.], v. 7, n. 3.29, p. 769–774, 2018. DOI: 10.14419/ijet.v7i4.29.21656. Disponível em: https://sciencepubco.com/index.php/IJET/article/view/21656.. Acesso em: 15 apr. 2025.