MARIA DOMINIC SAVIO, M; BONASU, Anudeep; GOSWAMI, Sanjeevan; N S RESHMA, K. Low Power Clock Gated Delay Buffers. International Journal of Engineering and Technology, [S. l.], v. 7, n. 3.34, p. 882–884, 2018. DOI: 10.14419/ijet.v7i3.34.19581. Disponível em: https://sciencepubco.com/index.php/IJET/article/view/19581.. Acesso em: 28 apr. 2025.