KUMAR PATEL, Beerendra; KANUNG, Jitendra. Diminished-1 multiplier using modulo adder. International Journal of Engineering and Technology, [S. l.], v. 7, n. 4.20, p. 31–35, 2018. DOI: 10.14419/ijet.v7i4.20.22117. Disponível em: https://sciencepubco.com/index.php/IJET/article/view/22117.. Acesso em: 18 apr. 2025.