Sasipriya P, S Kanchana Bhaaskaran V. Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL). IJET [Internet]. 2018 Jul. 19 [cited 2025 Apr. 7];7(3):1548-51. Available from: https://sciencepubco.com/index.php/IJET/article/view/14632