Effect of electron mobility variation on short channel effects in nanoscale double gate FinFETs: A comparative study

  • Authors

    • Nura Muhammad Shehu Department of Physics, Bayero University Kano,
    • Garba Babaji Department of Physics, Bayero University, Kano, Nigeria
    • Mutari Hajara Ali Department of Physics, Bayero University, Kano, Nigeria
  • DIBL; Electron Mobility; FinFETs, SCEs, GaAs, GaSb.
  • This work investigates the impact of electron mobility variations on short channel effects (SCEs) in different semiconductor materials using FinFETs. Using PADRE simulator, the work examines Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN), and Silicon (Si) FinFETs, analyzing performance metrics such as Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS) and Threshold Voltage roll-off. The result shows that GaN-FinFET exhibits lowest subthreshold swing of 63 mV/dec at electron mobility of 10000 cm2/Vs, and threshold voltage of 0.44V at electron mobility of 10000 cm2/Vs, while Si-FinFET exhibits lowest DIBL of 3 mV/V at (4000-10000) cm2/Vs. This finding contributes to advancing the understanding of short channel effects in nanoscale FinFETs and provides valuable insights for optimizing device performance in future semiconductor technologies.

  • References

    1. S. K. Dargar and V. M. Srivastava, “Performance Analysis of 10 nm FinFET with Scaled Fin-Dimension and Oxide Thickness,” 2019 Int. Conf. Autom. Comput. Technol. Manag. ICACTM 2019, pp. 1–5, 2019, https://doi.org/10.1109/ICACTM.2019.8776710.
    2. S. Mangesh, P. K. Chopra, and K. K. Saini, “Quantum effect in Nanoscale SOI FINFET device structure: A simulation study,” Proc. 2nd Int. Conf. 2017 Devices Integr. Circuit, DevIC 2017, pp. 795–798, 2017, https://doi.org/10.1109/DEVIC.2017.8074062.
    3. P. Wambacq et al., “The potential of FinFETs for analog and RF circuit applications,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 54, no. 11 SPEC. ISS., pp. 2541–2551, 2007, https://doi.org/10.1109/TCSI.2007.907866.
    4. E. H. Minhaj, S. R. Esha, M. M. R. Adnan, and T. Dey, “Impact of Channel Length Reduction and Doping Variation on Multigate Fin-FETs,” 2018 Int. Conf. Adv. Electr. Electron. Eng. ICAEEE 2018, pp. 1–4, 2019, https://doi.org/10.1109/ICAEEE.2018.8642981.
    5. S. Zhang, “Review of Modern Field Effect Transistor Technologies for Scaling,” J. Phys. Conf. Ser., vol. 1617, no. 1, 2020, https://doi.org/10.1088/1742-6596/1617/1/012054.
    6. K. VinayakPrakash, A. Kumar, and P. Jain, “Circumventing Short Channel Effects in FETs: Review,” Int. J. Comput. Appl., vol. 117, no. 17, pp. 24–30, 2015, https://doi.org/10.5120/20648-3407.
    7. D. Bhattacharya and N. K. Jha, “FinFETs: From devices to architectures,”Advances in Electronics, vol. 2014, pp. 21–55, 2015, https://doi.org/10.1017/CBO9781316156148.003.
    8. R. M. Asif, S. U. Rehman, A. U. Rehman, M. Bajaj, S. Choudhury, and T. P. Dash, “A Comparative Study of Short Channel Effects in 3-D FinFET with High-K Gate Di-electric,” 2021 Int. Conf. Adv. Power, Signal, Inf. Technol. APSIT 2021, no. December, 2021, https://doi.org/10.1109/APSIT52773.2021.9641388.
    9. A. F. Roslan et al., “30nm DG-FinFET 3D construction impact towards short channel effects,” Indones. J. Electr. Eng. Comput. Sci., vol. 12, no. 3, pp. 1358–1365, 2018, https://doi.org/10.11591/ijeecs.v12.i3.pp1358-1365.
    10. G. Saini and A. K Rana, “Physical Scaling Limits of FinFET Structure: A Simulation Study,” Int. J. VLSI Des. Commun. Syst., vol. 2, no. 1, pp. 26–35, 2011, https://doi.org/10.5121/vlsic.2011.2103.
    11. M. Kailasam and M. Govindasamy, “Impact of high-k gate dielectrics on short channel effects of dg n-finfet,” Int. J. Sci. Technol. Res., vol. 9, no. 3, pp. 2023–2026, 2020.
    12. M. Mustafa, T. A. Bhat, and M. R. Beigh, “Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology,” World J. Nano Sci. Eng., vol. 03, no. 01, pp. 17–22, 2013, https://doi.org/10.4236/wjnse.2013.31003.
    13. G. R. Murthy, S. Tiwari, and S. Marasu, “IMPACT OF DIELECTRIC MATERIALS ON FinFET CHARACTERISTICS AT 45nm US-ING SILVACO ATLAS 2-D SIMULATIONS,” Sci.Int.(Lahore), vol. 33, no. 1, pp. 61–64, 2021.
    14. S. Banerjee, E. Sarkar, and A. Mukherjee, “Effect of Fin Width and Fin Height on Threshold Voltage for Tripple Gate Rectangular Fin-FET,” TTIC, vol. 2, pp. 27–30, 2018.
    15. D. S. Bhargava, M. Sarumathi, and P. Venkatesh, “FinFET Technology : A Comparative Review of Traditional Transistors and FinFET based on performance metrics and physical dimensions,” Int. Journ. of Sci. Res in Comp. Sci. App. and Man. Stud., vol. 5, no. 6, 2016.
    16. Y. K. Ã, K. Tsutsui, K. Kakushima, P. Ahmet, V. R. Rao, and H. Iwai, “Analysis of Threshold Voltage Variation in Fin Field Effect Transistors : Separation of Short Channel Effects,”Japanese Journal of Applied Physics, vol. 044201, https://doi.org/10.1143/JJAP.49.044201.
    17. T. Irisawa et al., “Electron mobility and short-channel device characteristics of SOI FinFETs with uniaxially strained (110) channels,” IEEE Trans. Electron Devices, vol. 56, no. 8, pp. 1651–1658, 2009, https://doi.org/10.1109/TED.2009.2024029.
    18. C. H. Lin et al., “Channel doping impact on FinFETs for 22nm and beyond,” Dig. Tech. Pap. - Symp. VLSI Technol., pp. 15–16, 2012, https://doi.org/10.1109/VLSIT.2012.6242438.
    19. C. R. Manoj and R. Rao, “Impact of high-k gate dielectrics on the device and circuit performance of nanoscale FinFETs,” IEEE Elec-tron Device Lett., vol. 28, no. 4, pp. 295–297, 2007, https://doi.org/10.1109/LED.2007.892365.
    20. M. Poljak, V. Jovanović, and T. Suligoj, “Modeling study on carrier mobility in ultra-thin body FinFETs with circuit-level implica-tions,” Solid. State. Electron., vol. 65–66, no. 1, pp. 130–138, 2011, https://doi.org/10.1016/j.sse.2011.06.039.
    21. M. K. Rai, V. Narendar, and R. A. Mishra, “Significance of variation in various parameters on electrical characteristics of FinFET de-vices,” SCES 2014 Inspiring Eng. Syst. Glob. Sustain., vol. 1, pp. 2–7, 2014, https://doi.org/10.1109/SCES.2014.6880096.
    22. V. Subramanian et al., “Impact of fin width on digital and analog performances of n-FinFETs,” Solid. State. Electron., vol. 51, no. 4 SPEC. ISS., pp. 551–559, 2007, https://doi.org/10.1016/j.sse.2007.02.003.
    23. R. S. Pal, S. Sharma, and S. Dasgupta, “Recent trend of FinFET devices and its challenges: A review,” 2017 Conf. Emerg. Devices Smart Syst. ICEDSS 2017, no. March, pp. 150–154, 2017, https://doi.org/10.1109/ICEDSS.2017.8073675.
    24. Z. Lu and J. G. Fossum, “Short-channel effects in independent-gate FinFETs,” IEEE Electron Device Lett., vol. 28, no. 2, pp. 145–147, 2007, https://doi.org/10.1109/LED.2006.889236.
    25. A. Kumar and S. S. Singh, “Optimizing FinFET parameters for minimizing short channel effects,” Int. Conf. Commun. Signal Process. ICCSP 2016, pp. 1448–1451, 2016, https://doi.org/10.1109/ICCSP.2016.7754396.
    26. S. Xiong and J. Bokor, “Sensitivity of Double-Gate and FinFET Devices to Process Variations,” IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2255–2261, 2003, https://doi.org/10.1109/TED.2003.818594.
    27. S. Verma, S. L. Tripathi, and M. Bassi, “Performance Analysis of FinFET device Using Qualitative Approach for Low-Power applica-tions,” Proc. 3rd Int. Conf. 2019 Devices Integr. Circuit, DevIC 2019, no. August, pp. 84–88, 2019, https://doi.org/10.1109/DEVIC.2019.8783754.
    28. W. P. Maszara and M. R. Lin, “FinFETs - Technology and circuit design challenges,” Eur. Solid-State Device Res. Conf., pp. 3–8, 2013, https://doi.org/10.1109/ESSDERC.2013.6818808.
    29. A. Priydarshi and M. K. Chattopadhyay, “Low-Power and High-Speed Technique for logic Gates in 20nm Double-Gate FinFET Tech-nology,” J. Phys. Conf. Ser., vol. 755, no. 1, 2016, https://doi.org/10.1088/1742-6596/755/1/012055.
    30. S. Dwivedi and D. N. R. Prakash, “A Study on Recent Advancements in VLSI Technology using FinFETs,” Int. J. Innov. Res. Sci. Eng. Technol., vol. 12, no. 4, pp. 12788–12793, 2015.
    31. S. R. N. Yun, C. G. Yu, J. T. Park, and J. P. Colinge, “Quantum-mechanical effects in nanometer scale MuGFETs,” Microelectron. Eng., vol. 85, no. 8, pp. 1717–1722, 2008, https://doi.org/10.1016/j.mee.2008.04.023.
    32. E. M. Amin, M. Z. Baten, R. Islam, and Q. D. M. Khosru, “Quantum mechanical effect on determining threshold voltage of trigate Fin-FET using self-consistent analysis,” IEEE Reg. 10 Annu. Int. Conf. Proceedings/TENCON, no. 1, pp. 3–7, 2009, https://doi.org/10.1109/TENCON.2009.5396110.
    33. A. F. Roslan et al., “Comparative high-K material gate spacer impact in DG-finfet parameter variations between two structures,” In-dones. J. Electr. Eng. Comput. Sci., vol. 14, no. 2, pp. 573–580, 2019, https://doi.org/10.11591/ijeecs.v14.i2.pp573-580.
    34. A. Mahmood, W. A. Jabbar, Y. Hashim, and H. Bin Manap, “Effects of downscaling channel dimensions on electrical characteristics of InAs-FinFET transistor,” Int. J. Electr. Comput. Eng., vol. 9, no. 4, pp. 2902–2909, 2019, https://doi.org/10.11591/ijece.v9i4.pp2902-2909.
    35. E. Shang, Y. Ding, W. Chen, S. Hu, and S. Chen, “The Effect of Fin Structure in 5 nm FinFET Technology,” J. Microelectron. Manuf., vol. 2, no. 4, pp. 1–8, 2019, https://doi.org/10.33079/jomm.19020405.
    36. A. S. C. & S. M. M. A. M. Md. Javed Hossain, “Impacts of Variations in Channel Length, Width and Gate Work Function of Gan Fin-FET and Si-FinFET on Essential Electrical Parameters,” Int. J. Electr. Electron. Eng. Res., vol. 9, no. 2, pp. 29–42, 2019, [Online]. Available: http://www.tjprc.org/publishpapers/2-15-1572850801-4.IJEEERDEC20194.pdf.
    37. I. P. Buryk, A. O. Golovnia, M. M. Ivashchenko, and L. V. Odnodvorets, “Numerical simulation of FinFET transistors parameters,” J. Nano- Electron. Phys., vol. 12, no. 3, pp. 3–7, 2020, https://doi.org/10.21272/jnep.12(3).03005.
    38. Y. Sun, X. Yu, R. Zhang, B. Chen, and R. Cheng, “The past and future of multi-gate field-effect transistors: Process challenges and reli-ability issues,” J. Semicond., vol. 42, no. 2, 2021, https://doi.org/10.1088/1674-4926/42/2/023102.
    39. S. E. Huang, W. X. You, and P. Su, “Mitigating DIBL and Short-Channel Effects for III-V FinFETs with Negative-Capacitance Effects,” IEEE J. Electron Devices Soc., vol. 10, pp. 65–71, 2022, https://doi.org/10.1109/JEDS.2021.3133453.
    40. D. Jena, S. Das, A. Dastidar, and I. Engineering, “Performance comparison of GaN and Si FinFETs,” Jetir, vol. 9, no. 12, pp. 641–645, 2022.
    41. N. El, B. Hadri, and S. Patanè, “Effects of High-k Dielectric Materials on Electrical Characteristics of DG n-FinFETs,” Int. J. Comput. Appl., vol. 139, no. 10, pp. 28–32, 2016, https://doi.org/10.5120/ijca2016909385.
    42. M. S. Islam, M. S. Hasan, M. R. Islam, A. Iskanderani, I. M. Mehedi, and M. T. Hasan, “Impact of Channel Thickness on the Perfor-mance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding based Evaluation,” IEEE Access, vol. 9, pp. 117649–117659, 2021, https://doi.org/10.1109/ACCESS.2021.3106141.
    43. V. Kumar, R. Singh, R. Gupta, and R. Vaid , “Effect of High-k Gate Dielectric Materials on Electrical Characteristics of GaAs Channel Material Based Double Gate n-FinFET,” International Journal of Emerging Research in Management &Technology, vol. 9359, no. 8, pp. 51–56, 2016.
  • Downloads

  • How to Cite

    Shehu, N. M., Garba Babaji, & Mutari Hajara Ali. (2024). Effect of electron mobility variation on short channel effects in nanoscale double gate FinFETs: A comparative study. International Journal of Physical Research, 12(2), 24-28. https://doi.org/10.14419/n9r2ww08