Temperature-dependent short channel effects in nanoscale double gate FinFETs: A comparative study

  • Authors

    • Nura Muhammad Shehu Department of Physics, Bayero University Kano
    • Garba Babaji Department of Physics, Bayero University, Kano, Nigeria
    • Mutari Hajara Ali Department of Physics, Bayero University, Kano, Nigeria
    2023-12-20
    https://doi.org/10.14419/26gq9059

  • This work investigates the impact of temperature variation on Short Channel Effects (SCEs).  Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN) and Silicon (Si) are the channel materials that are investigated. The study examines phenomenal metrics such as Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), Threshold Voltage Roll-off, On-current and Transconductance using PADRE Simulator. The results revealed that GaAs-FinFET excels in terms of DIBL, threshold voltage, transconductance and on-current at higher temperatures. On the other hand, GaN-FinFET excels in terms of SS at lower temperatures. These findings contribute to the understanding of temperature effects on nanoscale double gate FinFETs, aiding their optimization for diverse electronic devices.

    Author Biographies

    • Garba Babaji, Department of Physics, Bayero University, Kano, Nigeria

      Professor

    • Mutari Hajara Ali, Department of Physics, Bayero University, Kano, Nigeria

      Professor

  • References

    1. Mahmood, W. A. Jabbar, Y. Hashim, and H. Bin Manap, “Effects of downscaling channel dimensions on electrical characteristics of InAs-FinFET transistor,” Int. J. Electr. Comput. Eng., vol. 9, no. 4, pp. 2902–2909, 2019, doi: 10.11591/ijece.v9i4.pp2902-2909. https://doi.org/10.11591/ijece.v9i4.pp2902-2909.
    2. H. Riel, L. Wernersson, M. Hong, and J. A. Alamo, “III – V compound semiconductor transistors — from planar to nanowire structures,” MRS Bulletin 39, pp. 668–677, 2014, doi: 10.1557/mrs.2014.137. https://doi.org/10.1557/mrs.2014.137.
    3. M. Kailasam and M. Govindasamy, “Impact of high-k gate dielectrics on short channel effects of dg n-finfet,” Int. J. Sci. Technol. Res., vol. 9, no. 3, pp. 2023–2026, 2020.
    4. R. S. Rathore and A. K. Rana, “Investigation of metal-gate work-function variability in FinFET structures and implications for SRAM cell design,” Superlattices Microstruct., vol. 110, pp. 68–81, 2017, https://doi.org/10.1016/j.spmi.2017.09.003.
    5. M. Kalasapati and S. L. Tripathi, “Robustness evaluation of electrical characteristics of sub-22 nm FinFETs affected by physical variability,” Mater. Today Proc., vol. 49, pp. 2245–2252, 2021, https://doi.org/10.1016/j.matpr.2021.09.336.
    6. E. H. Minhaj, S. R. Esha, M. M. R. Adnan, and T. Dey, “Impact of Channel Length Reduction and Doping Variation on Multigate FinFETs,” 2018 Int. Conf. Adv. Electr. Electron. Eng. ICAEEE 2018, pp. 1–4, 2019, https://doi.org/10.1109/ICAEEE.2018.8642981.
    7. G. R. Murthy, S. Tiwari, and S. Marasu, “IMPACT OF DIELECTRIC MATERIALS ON FinFET CHARACTERISTICS AT 45nm USING SILVACO ATLAS 2-D SIMULATIONS,” Sci.Int.(Lahore), vol. 33, no. 1, pp. 61–64, 2021.
    8. Gopinadh and A. George, “Variation in Parameters on Electrical Characteristics of FinFET with High-k dielectric,” Int. J. Adv. Res. Electr. Electron. Instrum. Eng. (An ISO, vol. 3297, pp. 8293–8299, 2007.
    9. N. El, B. Hadri, and S. Patanè, “Effects of High-k Dielectric Materials on Electrical Characteristics of DG n-FinFETs,” Int. J. Comput. Appl., vol. 139, no. 10, pp. 28–32, 2016, https://doi.org/10.5120/ijca2016909385.
    10. R. Saha, B. Bhowmick, and S. Baishya, “Deep insights into electrical parameters due to metal gate WFV for different gate oxide thickness in Si step FinFET,” Micro Nano Lett., vol. 14, no. 4, pp. 384–388, 2019, https://doi.org/10.1049/mnl.2018.5220.
    11. N. M. Shehu, M. H. Ali, and G. Babaji, “Performance Analysis of Nanoscale Double Gate Ge and GaSb finFETs,” Journ. of Sci. and Tech. Res., vol. 5, no. 2, pp. 322–330, 2023.
    12. T. A. Bhat, M. Mustafa, and M. R. Beigh, “Study of short channel effects in n-FinFET structure for Si, GaAs, GaSb and GaN channel materials,” J. Nano- Electron. Phys., vol. 7, no. 3, pp. 1–5, 2015.
    13. A. F. Roslan et al., “30nm DG-FinFET 3D construction impact towards short channel effects,” Indones. J. Electr. Eng. Comput. Sci., vol. 12, no. 3, pp. 1358–1365, 2018, https://doi.org/10.11591/ijeecs.v12.i3.pp1358-1365.
    14. B. Chugh, V. Narula, S. Lata, and B. Raj, “The effects of variation in geometry parameters on sub-50 nm finfet and their direct impact on finfet performance,” Proc. - 2nd Int. Conf. Intell. Circuits Syst. ICICS 2018, no. October, pp. 184–187, 2018, https://doi.org/10.1109/ICICS.2018.00045.
    15. F. Roslan et al., “Comparative high-K material gate spacer impact in DG-finfet parameter variations between two structures,” Indones. J. Electr. Eng. Comput. Sci., vol. 14, no. 2, pp. 573–580, 2019, https://doi.org/10.11591/ijeecs.v14.i2.pp573-580.
    16. S. E. Huang, W. X. You, and P. Su, “Mitigating DIBL and Short-Channel Effects for III-V FinFETs with Negative-Capacitance Effects,” IEEE J. Electron Devices Soc., vol. 10, pp. 65–71, 2022, https://doi.org/10.1109/JEDS.2021.3133453.
    17. A. S. C. & S. M. M. A. M. Md. Javed Hossain, “Impacts of Variations in Channel Length, Width and Gate Work Function of Gan FinFET and Si-FinFET on Essential Electrical Parameters,” Int. J. Electr. Electron. Eng. Res., vol. 9, no. 2, pp. 29–42, 2019, [Online]. Available: http://www.tjprc.org/publishpapers/2-15-1572850801-4.IJEEERDEC20194.pdf.
    18. S. I. et al. . Shafiqul Islam et al., “A Comparative Study of Sub-10nm Si, Ge and GaAs n-Channel FinFET,” Int. J. Semicond. Sci. Technol., vol. 7, no. 1, pp. 1–6, 2017, https://doi.org/10.24247/ijsstdec20171.
    19. M. S. Islam, M. S. Hasan, M. R. Islam, A. Iskanderani, I. M. Mehedi, and M. T. Hasan, “Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding based Evaluation,” IEEE Access, vol. 9, pp. 117649–117659, 2021, https://doi.org/10.1109/ACCESS.2021.3106141.
    20. S. Banerjee, E. Sarkar, and A. Mukherjee, “Effect of Fin Width and Fin Height on Threshold Voltage for Tripple Gate Rectangular FinFET,” TTIC, vol. 2, pp. 27–30, 2018.
    21. M. Mustafa, T. A. Bhat, and M. R. Beigh, “Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology,” World J. Nano Sci. Eng., vol. 03, no. 01, pp. 17–22, 2013, https://doi.org/10.4236/wjnse.2013.31003.

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    Nura Muhammad Shehu, Garba Babaji, & Mutari Hajara Ali. (2023). Temperature-dependent short channel effects in nanoscale double gate FinFETs: A comparative study. International Journal of Scientific World, 9(2), 25-30. https://doi.org/10.14419/26gq9059