Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation.


Introduction
Scaling of low power very large scale integrated circuits has boosted the sensitivity of CMOS circuits to produce large energy dissipation. Most of the energy is being washed out on the data buses and lengthy interconnects as dynamic power dissipation for charging and discharging of inter-wire capacitances and internal node capacitances. To improve on the whole performance of the application it is essential to control and reduce the technology scaling effects such as transition activity on data buses. One of the favorable techniques to increase the efficiency of the system is to encode the data on the bus. Hence this paper reviews several high performance encoding techniques to reduce transition activity, area and power dissipation.

Coding Scheme for Reduction of Power Dissipation
The importance of data coding technique is to reduce the data transition between data on parallel buses or neighboring data within the bus. Various research works carried out in reduction of power dissipation using data coding technique. Some of them are listed below. A Stan & Burleson [7] developed bus invert coding for Low power I/O. In this scheme entire buses are used for encoding purpose and include a redundant bit along with bit line. This scheme is simple and effectively reduces the switching activity. The bus invert method was explained in the meticulous location of dynamic input and output power dissipation the identical method can be useful in any case where huge capacitances are occupied.
Yoo & Choi (1999) suggested how to design low power reconfiguration of FPGAs using interleaving partial bus invert coding. The authors suggested a bus encoding scheme which partitions the data sequence into several sub sequences. After that reconfiguring FPGA partial bus invert coding algorithm is used in each and every sub sequence to diminish the amount of data bus transitions. The proposed method is very useful in massive reduction of bus transitions compared with the conventional bus invert coding such as partial bus invert coding and beach coding. Further, Partial bus invert coding is extended with decomposed bus invert coding technique for low power I/O buses recommended by Hong et al [32].In this work amount of bus transitions are reduced by innovative bus-invert coding scheme. Here, the bus positions are partitioned and each partitioned bus group is considered autonomously for reducing the overall transitions to get maximum efficiency. Results prove that the decomposed bus-invert coding scheme reduces the total number of bus transitions than the conventional and partial bus-invert coding algorithms in the same way.  (2002) developed bus invert coding for odd/even buses seperately for two phase transfer of buses with coupling effects. In this scheme the authors considered the numbered bus line and also coupling capacitances will charge and discharge by the activity of the neighbors. One line will be odd and the other neighbor line will be even. To reduce the coupling activity by independently controlling the odd and even bus lines with two separate lines, Odd Invert and Even Invert line to obtain significant reductions in power simply by comparing the coupling activity for the four possible cases of the Odd and Even Invert lines (00, 01, 10, 11), and then choosing the value with the smallest coupling activity to be transmitted on the bus. So after encoding, the transition for a pair of bus lines is still strongly dependents on data. The toggling sequences 01→10 and 10→01 result in 4 times more coupling energy dissipation than other coupling events.
Youngsoo & Takayasu (2002) have introduced model order reduction algorithm for analysis of power distribution in VLSI interconnects. The analysis and simulation effect induced by interconnects become progressively more essential as the scale of process technologies gradually shrinks. In this paper the power distribution study of interconnects is deliberated using reduced model algorithm. The difference between power utilization and the poles and residues of a transfer function is calculated and a simple accurate deriver model is also developed, for effective power computation. The existence of wire resistance ignored by the lumped capacitance model, which has been estimate the charging and discharging power consumption of CMOS circuits. During this study it was revealed that about 20% of the power is consumed in the wire resistance of the buffered global interconnect, when an interconnect is modeled with RC tree networks. The power distribution analysis of interconnect with RLC tree networks based on a reduced order model. The individual analysis of the driver circuits and the role of interconnect is much constructive to realize the sources of energy dissipation. Massimo et al [26] introduced energy consumption in RC tree circuits. In this paper, resistance, capacitance tree networks are modeled in terms of their energy consumption associated with an input transition. Based on Single pole approximation, the energy consumption circuits are modeled and equivalent time constant is also analytically derived from an exact analysis for very slow and very fast I/P transitions. Then this model is extended to arbitrary values of the input rise time by exploiting some intrinsic properties of RC tree networks. This method is fully analytical and leads to closed-form results. Transition skewing coding scheme proposed by Akl & Bayoumi [1] reduces power dissipation and area. This scheme deals with area, noise, cross talk, peak energy and signal integrity and switching and leakage power. The authors used 90nmtechnology to simulate. The encoded bus is compared against a standard bus and a bus with shields inserted between every two wires. The encoding and decoding latencies are also analyzed. Simulations show that transition skew coding is efficient in terms of energy and area with low encoding and decoding latency overhead. This work has been further extended in 90nm encoding scheme considering 2 GHz global clock frequency.  [14] have developed modified data encoding and decoding scheme for data transmission in network-on-chip. The main cause of dynamic power dissipation in network on chip is due to coupling capacitance and self-transition effects. The self-transition is decreased by examine the switching activity and then the coupling technique is included with the routed network, which is encoded by the network interface before they are injected in the network and are decoded by the destination network interface. The encoding scheme on a set of data showing that it is possible to reduce the power consumption for both self and coupling switching activity in an inter router links.

Coding Scheme for Reduction of Self and Coupling Transition
In CMOS circuits most power is dissipated as dynamic power due to switching transition during charging and discharging of load capacitance. Transition activity is classified in to self transition and coupling transition. In this field most of the research work analyzing coupling transition, self transition and combined both self and coupling transition techniques to reduce the power dissipation. Sumant et al [8] introduced a coding frame work for low power address and data busses presents a source coding frame work for design of coding schemes to reduce transition activity. In this frame work a data source is first passed through a decorrelating function f1 ,Next, a variant of entropy coding function f2 is employed, which reduces the transition activity. In this scheme incremental xor (inc-xor) method for address bus and probabilistic based mapping xor (xor-pbm) method for data bus is used to encode the data to reduce transition activity. Naveen et al [18] has implemented a new deep submicron bus encoding for low Energy. In present low power digital circuits the total amount of power scattered to wires is increasing day by day.
Reducing power dissipation in wires plays a major role in low power applications. Switching transitions meet the expense of momentous energy loss in deep sub-micron buses. As a conclusion this method reduces the coupling transitions activity for submicron technologies compared to the usual un-coded data lines. This process is adaptive it decreases the signal transmission for all sorts of data streams. Menon et al [27] introduced switching activity minimization in combinational logic design. The reduction of switching activity in combinational logic design an algorithmic way using karnaugh map has been proposed which modifies the normal optimal solution obtained from k-map to reduce its switching activity. More than 10% reduction in switching activity has been observed using this method. The final solution gives a good tradeoff between cost and power consumption. Tina et al (2004) have developed deep sub micron bus invert coding presents a deep sub micron bus invert coding for on chip parallel data buses. Similar to bus invert coding technique it is used to realize low complexity encoding and decoding circuitry, and with a complexity that scales linearly with the bus width. By introducing redundancy it is possible to reduce the energy dissipation in on chip parallel data buses. Muroyama et al introduced a variation aware low power coding methodology for tightly coupled buses. Variable length coding is proposed to reduce the self capacitance and switching power. Probabilistic information is used to for assigning the code. The smaller length code is assigned for more frequent data, in which the major sources of the power consumption are the activities on the signal lines and the coupling capacitances of the In recent year's low power and power awareness has become a major driving force especially due to portable electronics and the growing cost of the power dissipation. DSM bus power dissipation is directly related to the switching activity of the coupling capacitance that exist between the bus lines and also the switching activity of the self capacitance present between the bus interconnect and the ground. The technique used here is to reduce the switching activity of both self and coupling capacitances through encoding the data on buses. Mullainathan & Ramkumar [19] proposes switching reduction through data encoding techniques in Network on chip. Here encoding scheme is used to reduce the power dissipation and the energy consumption of the communication system in NoC. Onchip interconnect has more significant fraction of the overall system power/energy budget. So in the definition of new methodologies and techniques aimed at optimizing the on chip communication system not only in terms of performance but also in power. The method followed is, encoding the packets before they are injected into the network in such a way as to minimize both the switching activity and the coupling transition effects in the NoC's links which represent the main factors of power dissipation. Devendra Kumar et al [34] have introduced FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects based on FDTD analysis of transition time effects on crosstalk. The investigation carried out is for equal and unequal transition times. The unequal rise time effects are also equally important because, it is common to have mismatch in the rise time of the signals transmitting through different wire length. As an example, two distributed RLC lines coupled inductively and capacitive are considered. The FDTD method is followed because it gives accurate results and carries time domain analysis of coupled lines.

Conclusion
In this review paper, various encoding schemes have been reviewed. it is observed that with the rise in VLSI technology , complexity of encoding have increased . The main emphasis of different researches is to reduce the signal transition in the bus. Area and different type of transition activity like self transition and coupling transition are the main cause of dynamic power dissipation. Researchers have suggested various encoding methods to reduce self and coupling transition effects from micrometer to nanometer technology.