Analysis of a three phase capacitor voltage balanced hybrid multi-level inverter with a three phase RL-load

This paper outlined the basic concepts of two selected types of hybrid multi-level inverters that were capacitor voltage-source dependent. A natural capacitor voltage balancing involving hysteresis with redundant switching states was analyzed in this paper. Simulations using MATLAB 7.14 were carried out for an unbalanced and a well-balanced capacitor voltage supply under 0V, 100V and 200V pre-charged capacitor voltage conditions. A comparative analysis of the two types of hybrid multi-level inverters (Type A and Type B) with pertinent to %THD values of [35.77% and 23.79%] for Type A and [92.10% and 84.94%] for type B during fault occurrence were evaluated in this work. These harmonic values can lead to thermal run away and total malfunction of the semi-conductor switches. An experimental validation of Type A hybrid multi-level inverter with a three level flying capacitor input stage and H-bridge output stage using a three phase RL-Load of 15Ω and 45mH was accomplished in the laboratory with results compared with the simulations for experimental verification.


Introduction
Capacitor voltage balancing is one of the major challenges for modular multilevel converters (MMC's). To generate a precise five voltage levels for a capacitor fed voltage source inverter, it is important to keep the voltage of the D.C capacitors balanced. The flying capacitor voltage can be balanced by appropriate selection of the redundant switching states. To balance the D.C link capacitor voltages, many dc capacitor voltage balancing techniques have been proposed in literature. Reference [1] presented a voltage balancing method for a novel diode clamped modular multilevel converter, but it requires an external energy feedback circuit and high switching frequency which led to lots of losses. A model predictive control strategy was presented in [2] to carry out the capacitor voltage balancing of the modular multilevel converters with reduced switching frequency. Reference [3] introduced a voltage balancing control for modular multilevel converters at fundamental switching frequency where the pulse-widths were the same but the phase angles were different in each fundamental frequency period. In this reference, voltage balancing was realized by shifting the pulses in sequence in each fundamental frequency period. This however needs a several number of periods for capacitor voltage balancing. The technique of zero-sequence voltage injection was used to balance the dc-link capacitor voltages and was reported in [4]. In this reference, the zero sequence voltage did not influence the output line voltage and current but it led to different pulse pattern and different neutral-point current. The main problem with this method was that the calculation and selection of zero sequence voltage was very complex and the switching frequency was not always constant with phase disposition pulse width modulation. A control strategy based on Selective-Harmonic Elimination (SHE) PWM was proposed in [5]. The voltage across the flying capacitor clamped was balanced by swapping the switching patterns. The swapping of the switching patterns depended on the polarity of the output current and the polarity of the flying capacitor voltage. The dc-link capacitor voltage was regulated by adding or subtracting a relatively small pulse to the switching pulse signals. That method was very suitable for high power and low switching frequency applications. However, the voltage regulation ability was not strong due to the low switching frequency and high capacitor voltage ripple. The space vector modulation (SVM) was proposed in [6]. The SVM was used to generate five-level output voltage and to balance the voltages of the dc-link capacitors and flying capacitor (FC). For a five level SVM method, there are 125 space vectors in total for the output voltage synthesis. Each space vector represented one possibility of switch combination, and each space vector has different impact on dc capacitor and FC voltage variation. the field distribution of the stator. As a result, the singly excited induction machine is capable of producing torque at any speed below synchronous speed. For this reason, induction machines are placed in the class of asynchronous machines. The SVM method was divided into different categories of triangles. Each category has its own principles to choose the vector sequence and compute the vector durations based on the dc capacitor voltage difference. The key problem of this method was the complicated calculation process. Similar to the zero sequence voltage injection method, the SVM balancing technique can only be used in three phase applications. A dc link capacitor voltage balancing technique based on phase disposition pulse width modulation for single phase application was proposed in [7]. The basic idea is changing the flying capacitor reference voltage to change the dc capacitor voltages. The problem of this method was that the flying capacitor voltage will have double of the line frequency ripple in steady state which will increase the output current THD. In addition, the dynamic response of regulating the dc link capacitor voltages is not always desirable. In [8], a capacitor voltage balancing method for the modular multilevel converter with the switching frequency as grid frequency was proposed. In this reference, the low switching frequency can effectively reduce excess switching loss though the drive pulses have different pulse-widths but the same phase angle in each switching period. Based on the reviewed literature, it was observed that the existing dc balancing techniques were only suitable for three phase applications; while for single phase applications, the existing technologies have many problems such as high flying capacitor voltage ripple, slow dynamic response. This paper, thus applied the concept of hysteresis voltage band for capacitor voltage balance for a single phase and a three phase topology with a phase disposition modulation at a reduced capacitor voltage ripples. The hysteresis voltage band ∆V was usually set to a very small percentage of the actual capacitor voltage V F1 . The upper band applied in this work was denoted by V h1 = V F1 (1 + ∆V 2 ) while the lower band is denoted by V n1 = V F1 (1 − ∆V 2 ).

Capacitor voltage balancing for type a hybrid multi-level inverter
Many hybrid multi-level inverters have been proposed in reputable literatures. A considerable number of hybrid multi-level inverters were derived from the combinations of one or more conventional multi-level inverters [9]- [12]. The two capacitor voltage balanced hybrid multilevel inverters considered in this paper were classified as Type (A) and Type (B). Type (A) consists of Five-Level Inverter formed from three level flying capacitor as an input and H-bridge as an output while Type (B) is a Five-Level actively neutral point clamped inverter with one flying capacitor as an output. Type (A) hybrid multilevel inverter was shown in Figures 1 and 2. An important feature of this inverter topology was the ability to operate with one source of dc voltage supply. A more prominent feature when compared with other topologies was the ability to operate in three-level mode at full power rating when one of the devices in the H-bridge fails. At this condition, the H-bridge was bypassed through a fast bypass switch or by routing the current through the devices in the complementary path. This feature of the inverter improved the reliability of the whole system thus ensuring continuity in operation and fault-tolerant at all conditions. The modulation scheme was simple and did not need a complex modulation control strategy for the capacitor voltage balancing. The control strategy was based on a multicarrier level shifted in-phase disposition pulse width modulation and a hysteresis capacitor voltage band that regulated the level of capacitor voltage deviation. The three-level flying capacitor was set to a reference voltage value of V c1r = V dc 2 while the H-bridge capacitor reference voltage was set to V c2r = V dc 4 . Table 1 shows the sixteen switch states, inverter output voltage levels with the charging and discharging condition of the capacitor for the Type A hybrid inverter. In Table 1, the capacitor voltage balancing was achieved with different redundant switch states. Three redundant switch states (5,9,14) at Step One: For Positive Load Current (i a > 0) and V 0 = V dc 4 , i). Switch state 14 was chosen if capacitor C2 was undercharged by V c2 ≤ (V c2r − dV) and needed to be charged to its acceptable voltage range of (V c2r − dV) < V c2 < (V c2r + dV) where dV was the permissible voltage deviation from the flying capacitor reference voltage. ii). Else switch state 9 was chosen if capacitor C2 was overcharged by V c2 ≥ (V c2r + dV) and needed to be discharged to its permissible voltage range and capacitor C1 was undercharged by V c1 ≤ (V c1r − dV) and needed to be charged to its permissible voltage range of (V c1r − dV) < V c1 < (V c1r + dV) iii). Else switch state 5 was chosen if capacitor C2 was overcharged by V c2 ≥ (V c2r + dV) and needed to be discharged to its permissible voltage range and capacitor C1 was overcharged by V c1 ≥ (V c2r + dV) and needed to be discharged to its permissible voltage range.
Step Two: For Negative Load Current (i a < 0) and V 0 = V dc 4 , i). Switch state 14 was chosen if capacitor C2 was overcharged by V c2 ≥ (V c2r + dV) and needed to be discharged to its permissible voltage range. ii). Else switch state 9 was chosen if capacitor C2 was undercharged by V c2 ≤ (V c2r − dV) and needed to be charged to its permissible voltage range of (V c2r − dV) < V c2 < (V c2r + dV) and capacitor C1 was overcharged by V c1 ≥ (V c1r + dV) and needed to be discharged to its permissible voltage range. iii). Else switch state 5 is chosen if capacitor C2 is undercharged by V c2 ≤ (V c2r − dV) and needs to be charged to its permissible voltage range of (V c2r − dV) < V c2 < (V c2r + dV) and capacitor C1 is undercharged by V c1 ≤ (V c1r − dV) and needs to be charged to its permissible voltage range. The same control procedure for positive and negative load current direction for V 0 = V dc 4 , was applied when V 0 = 0, and V 0 = − V dc 4 for efficient capacitor voltage balance control algorithm. In Figure 1, when a fault occurred at the H-bridge, the five level inverter operated normally by producing a full three level voltage at maximum power. This action was usually achieved by bypassing the H-bridge to ensure continuity as shown in Figure 2. This unique characteristic differentiates it from other topologies.
In Table 1, out of the fifteen output voltage states, -3Vdc/4 and 3Vdc/4 were not applied since they do not have redundant switching states to balance the capacitor voltage. For an unbalanced capacitor voltage condition, the five level voltage waveform tends to change in symmetry after a given cycle. Figure 3 shows two capacitors and an inverter output voltages under an unbalanced capacitor voltage control for per cycle switch state sequence (s a1 , s a2 , s a3 , s a4 ) of 1111 → 1110 → 1000 → 0001 → 0011 (switching state number 15 → 14 → 08 → 01 → 03 of Table 1). In Figure  3, it was observed that the capacitor C2 voltage rised to a higher value than its reference value of V c2r = V dc 4 . The same goes for C1 with a reference value of V c1r = V dc 2 for V dc = 200V. That made the inverter output voltage highly distorted and far from being the desired five level output. For a balanced capacitor voltage condition, the five-level voltage waveform tends to trace the shape of the reference voltage and maintain a given symmetry after a given cycle. Figure 4 shows that capacitors C1 and C2 voltages (Vc1 and Vc2), in relatively fast response time becomes balanced and essentially equal to their respective reference voltages of V c1 ≈ V c1r =         Figure 2, the H-bridge is bypassed and the inverter operates in three-level mode producing the same full voltage magnitude and full power output which was equivalent to the ratings of the five-level operation. The results shown in Figures 13-15 confirm this concept.

Capacitor voltage balancing for type b hybrid multi-level inverter
Type (B) hybrid multilevel inverter was shown in Figures 16 and 17. The circuit diagram presented in Figure 16 depicts the single phase five-level active neutral point clamped (5L-ANPC) hybrid inverter topology. This converter was an arrangement of two level inverters connected in parallel with the d.c-link capacitors. The first sub-circuit was made up of bidirectional switches S5, S6, S9, S10, with a capacitor C2. The second sub-circuit was made up of bidirectional switches S7, S8, S11, S12, with a capacitor C3 while the third sub-circuit was made up of bidirectional switches S1, S2, S3, S4, with a capacitor C1 which was used to connect the converter to the output phase. It was worth mentioning that the switches S5, S7 and S6, S8 were operated in phase. S5 and S7 were complementary to S6 and S8. A similar sequence was applied to S9, S10, S11 and S12.The three floating capacitors shown in Figure 16 add more cost to the overall system and require more space for accommodating the entire volume of the inverter structure. For this reason, it was expedient to reduce the number of floating capacitors in terms of component count. This was achieved by removing C2 and C3 from Figure 16 to form a more reduced circuit as shown in Figure  17 which was a simplified diagram for three phase 5Level-ANPC. The possible switching states for the discussed 5Level-ANPC was presented in Table 2 with capacitors C1, C2 and C3 charged to a voltage level of  The five-level ANPC inverter has one capacitor. A capacitor voltage band of Vh1 = 101.5 V and Vn1 = 99.5 V was set up to track the expected output voltage. This reduced the control complexity in the capacitor voltage balance [13]- [14]. The output voltage can easily be synthesized with the sequence reported in [15]- [20]. The following steps were considered for the switching combinations for the Type (B) hybrid multi-level inverter under a balanced capacitor voltage technique.
Step 1: For VAO = + V dc 2 . Switches S a5, S a3, and S a1 were turned on. The output current i a under positive and negative mode has no effect on C1.
Step 2: For the Positive Load Current i a > 0 and V 0 = V dc 4 , i). If switches Sa5, Sa3 and Sa2 were turned on, capacitor C1 was undercharged by V c1 ≤ (V c1r − dV) and will be charged to its allowable voltage range of (V c1r − dV) < V c1 < (V c1r + dV). Where dV was the maximum allowable voltage deviation from the flying capacitor reference voltage. ii). Else, switches Sa7, Sa4 and Sa1 were turned on with capacitor C1 overcharged by V c1 ≥ (V c1r + dV) and will be discharged to its allowable voltage range of V c1 ≤ (V c1r + dV). Where dV was the permissible voltage deviation from the flying capacitor reference voltage.
Step 3: For Negative Load Current i a < 0 and V 0 = V dc 4 , i). If switches Sa5, Sa3 and Sa2 were turned on, capacitor C1 was overcharged by V c1 ≥ (V c1r + dV) and will be charged to its allowable voltage range of V c1 ≤ (V c1r + dV). ii). Else, Sa7, Sa4 and Sa1 were turned on with capacitor C1 undercharged by V c1 ≤ (V c1r − dV) and will be charged to its allowable voltage range of (V c1r − dV) < V c1 < (V c1r + dV).
Step 4: For the Positive Load Current i a > 0 and V 0 = 0, When switches Sa6, Sa3 and Sa1 or Sa7, Sa4 and Sa2 were on, capacitor C1 was unaffected by i a .
Step 5: For the Negative Load Current i a < 0 and V 0 = 0, When switches Sa6, Sa3 and Sa1 or Sa7, Sa4 and Sa2 were on, capacitor C1 was unaffected by i a .
Step 6: For the Positive Load Current i a > 0 and V 0 = − V dc 4 , i). If switches Sa6, Sa3 and Sa2 were turned on, capacitor C1 was undercharged by V c1 ≤ (V c1r − dV) and will be charged to its allowable voltage range of (V c1r − dV) < V c1 < (V c1r + dV). ii). Else, switches Sa8, Sa4 and Sa1 were turned on with capacitor C1 overcharged by V c1 ≥ (V c1r + dV) and will be discharged to its allowable voltage range of V c1 ≤ (V c1r + dV).
Step 7: For Negative Load Current i a < 0 and V 0 = − V dc 4 , i). If switches Sa6, Sa3 and Sa2 were turned on, capacitor C1 was overcharged by V c1 ≥ (V c1r + dV) and will be discharged to its allowable voltage range of V c1 ≤ (V c1r + dV). ii). Else, Sa8, Sa4 and Sa1 were turned on with capacitor C1 undercharged by V c1 ≤ (V c1r − dV) and will be charged to its allowable voltage range of (V c1r − dV) < V c1 < (V c1r + dV).
Step 8: For VAO = −V dc 2 , S a8, S a4, and S a2 were turned on. The current output i a has no effect on the capacitor (C1). The pairs of redundant switching states were used to balance the capacitor voltage. Thus proper selection of the redundant switching states balances the flying capacitor (FC) voltage. This implied that the 5L-ANPC combined the robustness of the NPC with the flexibility of the flying capacitor.  with two redundant switch states (6 and 7). These two combinations provided self-controlled capacitor voltage balancing. The self-balancing implied that the natural balancing control algorithm was not applied. This can be achieved if either the per cycle switch state sequence of 1 → 2 → 4 or 5 → 6 → 8 and 1 → 3 → 4 or 5 → 7 → 8 in Table 2 were applied on the inverter switches. For self-balancing (with no balancing control) operation, the circuit dynamic response becomes relatively slow because of the relatively large value of capacitor C 1 of 7500µF needed to maintain the steady state capacitor voltage ripple to an appreciable low level. The waveforms for the capacitor voltage (V cf ) and the inverter output voltage (V an ) under self-capacitor voltage balancing operation without a balancing control algorithm was shown in Figures 18-19.  When capacitor voltage balancing control as earlier discussed was applied to the Five-level ANPC circuit diagram of Figure 17, the capacitor voltage becomes balanced. The circuit dynamic response becomes relatively fast in response time due to the relatively small value of capacitor C 1 of 1500µF needed to maintain the steady state capacitor voltage ripple to an appreciable low level. The capacitor voltage was then made equal to its reference voltage value of V cf ≈ V cfr = V dc 4 = 50 V for V dc = 200 V as shown in Figure 20 for Vcf and Van. Similarly, when a pre-charged capacitor voltage values of 0 V and 100 V with a Vdc of 400 V were applied for a natural capacitor voltage balance control the results presented in Figures 19 -22 were realized.     In line with the fault tolerant condition, when the ANPC capacitor was shorted, the inverter produced a highly distorted and unsymmetrical waveforms. Though maximum power was produced which is similar to the type A hybrid topology, that was less efficient due to distortions and high harmonics (%THD of 92.10 and 84.94) as shown in Figures 25-26.

Experimental set up for type a hybrid multi-level inverter
The experemental set up was shown in Figure 27. This is made up of four stages. The first stage was the d.c power supply which consists of a coiled 1.5 kVA, 220/200 Volts transformer, nine 100 Amps full bridge diode rectifiers and 2200 µF, 200 Volts capacitor filters. The second stage consists of the firing pulses or gate signal generator using EZDSPTMF28335 digital signal processor (dsp). The pulses generated from the dsp were processed using the dc-dc converter (VAS D1-S12-D12) which amplifies the generated signals that drives the power switches. The third stage was the dead band (1milisecond) or the isolation circuit which was achieved with a variable resistor of 10 kΩ and a capacitor value of 0.1µF. The fourth stage was the RL-load design calculation which involves a 1000 Watts power output, a 45 0 power factor angle and a 200 Vrms. A power triangle was applied to determine the values of R = 15 Ω, L = 45 mH and Z = 20 Ω. The block diagram in Figure 27 depicts the inverter d.c power supply unit.

Simulation results and discussion
The capacitor voltages and inverter output voltage for an unbalanced capacitor state of Type A Hybrid multi-level inverter with V dc = 200V was presented in Figure 3. It was observed that the capacitor voltages (V c1 and V c2 ) raised to a higher value than the reference value of V c1r = V dc 2 and V c2r = V dc 4 . This exponential rise in the capacitor voltage made the inverter output highly distorted and above the desired five level inverter output voltage. Figure 4 showed a well-balanced capacitor voltage. It was obvious that the capacitor voltages (V c1 and V c2 ) in Figure 4 were equal to the reference value of V c1r = V dc 2 = 100V and V c2r = V dc 4 = 50 V for V dc = 200 V. In Figure 5, when V dc = 400V, the capacitor voltages V c1 and V c2 were balanced at a value of V c1 = 200 V and V c2 = 100 V. The transient period of 0 -0.1second indicated the charging period of the capacitor when the pre-charged capacitor voltage was set at zero as shown in the inverter output current and voltage. Figure 6 represents a balanced capacitor voltage waveform when a pre-charged capacitor voltage values of 100 V and 200 V were impressed on the capacitors. It was observed that the transience was diminished and the inverter output current and voltage maintained a stable state from 0 -0.4second. In Figures 7-12, the per phase voltage and the line-line voltages were represented with a corresponding %THD for pre-charged voltage values of 100 V and 200 V. A close observation indicated that a stable voltage was maintained all through the simulation period with close %THD values. In Figures 13-15, it was proven that the H-bridge was bypassed during a fault occurrence on the H-bridge. The inverter operated in three-level mode producing the same full voltage magnitude of 200 V for the phase voltage and 400 V for the line voltage which was equivalent to the voltage ratings of the full five-level inverter in Figures 7 and 10. In Figures 18 and 19, the unbalanced capacitor voltage states for type B Hybrid multi-level inverter with V dc = 200 V were presented. It was observed that the dynamic response was relatively slow due to the large value of capacitor (7500µF) needed to maintain the steady state capacitor voltage ripple to an appreciable low level. The capacitor voltage under this condition was not equal to the reference voltage value V cf ≠ V cfr ≠ V dc 4 . In Figure 20, the capacitor voltage was balanced for type B Hybrid Multi-Level Inverter. The dynamic response in Figure  20 was relatively fast in response time due to the small value of capacitor (1500µF) needed to maintain the steady state capacitor voltage ripple to a low level. At this condition, V cf ≈ V cfr = V dc 4 = 50 V for V dc = 200 V. In Figure 21, the capacitor voltage V cf for V dc = 400 V

Experimental results and discussion
The stiff dc voltage from the 2200µF, 200 V capacitor was presented in Figure 28. The five-level output phase voltages were presented in Figures 29 and 30 at modulation indices of 1.2 and 0.8 respectively. The five-level line voltages at a modulation index of 0.8 were presented in Figures 31 and 32. The three phase current was presented in Figure 33. As earlier stated in the simulation results of Figures 14 and 15, when an H-bridge was bypassed, a three-level voltage was produced. The waveform generated from the laboratory result when an H-bridge was bypassed was shown in Figure 34

Conclusion
Hybrid multi-level inverters (Types A and B) were analyzed under an unbalanced and a well-balanced capacitor voltage condition. The rate of rise in the capacitor voltage deviation from the reference voltage value was investigated for 0V, 100V and 200V pre-charged capacitor voltage values. The transient response of the capacitor voltage with pertinent to the above pre-charged condition was also analyzed. The dynamic response of the capacitor voltage in relative speed to changes in the capacitor values from 7500 µF to 1500 µF was discussed. The effects of faults occurrence on the two types of the hybrid multilevel inverters were underscored. The fault analysis indicated that type B five-level ANPC inverter albeit producing a three-level inverter waveforms of the same voltage magnitude and power rating of a five-level generates more harmonic values of 92.10% and 84.94%. These harmonic values can lead to thermal run away and total malfunction of the semi-conductor switches. Similarly, type A hybrid inverter under fault occurrence on the H-bridge produced a three-level inverter waveforms of the same voltage magnitude and power rating of a five-level but generates less harmonic values of 35.77% and 23.79%. The experimental results carried out and presented in Figures 34, 35 and 36 under a bypassed H-bridge showed that a close similarity exist between the simulated results presented in Figures 14 and 15 which validates the research paper.