Effect of radius on various parameters of cylindrical surrounding double-gate (CSDG) MOSFET

  • Authors

    • Okikioluwa E. Oyedeji School of Electrical, Electronic and Computer Engineering,University of KwaZulu-Natal,Howard College CampusDurban - 4041, South Africa.
    • Viranjay M. Srivastava School of Electrical, Electronic and Computer Engineering,University of KwaZulu-Natal,Howard College CampusDurban - 4041, South Africa.
    2018-09-10
    https://doi.org/10.14419/ijet.v7i4.10110
  • CSDG MOSFET, Carrier Mobility, Drift-Diffusion Component, Nanotechnology, Pao-Sah Integral, Transconductance, VLSI.

  • Abstract

    The MOSFET is an integral component of electronics device and scaling the device is continuously in progress. This research work intro-duces a novel structure of the Cylindrical Surrounding Double-Gate (CSDG) MOSFET to improve scaling and to suppress Short Channel Effect (SCE). In order to achieve this improvement, the drift-diffusion components are used to analyze the drain current of the device through the Pao-Sah integral. Then transconductance is derived to indicate an improved performance of the proposed design. The capaci-tance characteristics of this MOSFET is also analyzed through the equivalent capacitance model as well as the analysis of the carrier mobility, in which it has been observed that scaling of the device supports increase in mobility of the charge carrier.

     

     

  • References

    1. [1] Sung R. Jang, Hong J. Ryoo, Gennadi Goussev, and Geun H. Rim, “Comparative study of MOSFET and IGBT for high repetitive pulsed power modulators,†IEEE Transactions on Plasma Science, vol. 40, no. 10, pp. 2561-2568. Feb. 2012. https://doi.org/10.1109/TPS.2012.2186592.

      [2] Yuan Taur and Tak H. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, 2013.

      [3] Eckart Hoene, Andreas Ostmann, and Christoph Marczok, “Packaging very fast switching semiconductors,†8th International Conference on Integrated Power Systems 2014, Nuremberg, Germany, 25-27 Feb. 2014, pp. 1-7.

      [4] Jianjing Wang, Henry S. Chung, and River T. Li, “Characterization and experimental assessment of the effects of parasitic elements on the MOSFET switching performance,†IEEE Transactions on Power Electronics, vol. 28, no. 1, pp. 573-590, April 2012. https://doi.org/10.1109/TPEL.2012.2195332.

      [5] Keith R. Green and Jerry G. Fossum, “A simple two-dimensional model for subthreshold channel-length modulation in short-channel MOSFETs,†IEEE Transactions on Electron Devices, vol. 40, no. 8, pp. 1047-1053, Aug. 1993. https://doi.org/10.1109/16.223724.

      [6] Kurt Lehovec and W. G.Seeley, “On the validity of the gradual channel approximation for junction field effect transistors with drift velocity saturation,†Solid-State Electronics, vol. 16, no. 9. pp. 337-350, Sept. 1973. https://doi.org/10.1016/0038-1101(73)90206-2.

      [7] Geoffrey W. Taylor, “Subthreshold conduction in MOSFETâ€, IEEE Transactions on Electron Devices, vol. 25, no. 3. pp. 337-350, March 1978. https://doi.org/10.1109/T-ED.1978.19079.

      [8] Kwok Ng, Ali Eshraghi, and Tom Stanik, “An improved generalized guide for MOSFET scaling,†IEEE Transactions on Electron Devices, vol. 40, no. 10, pp. 1895-1897, Oct. 1993. https://doi.org/10.1109/16.277356.

      [9] Subha Subramaniam, R. Wale, and Sangeeta M. Joshi, “Drain current models for Single-Gate MOSFETs, undoped symmetric and asymmetric double-gate SOI MOSFETs and quantum mechanical effects: A review,†International Journal of Engineering Science and Technology, vol. 5, no. 1, pp. 96-105, Jan. 2013.

      [10] Samar K. Saha, “Managing technology CAD for competitive advantage: An efficient approach for integrated circuit fabrication technology development,†IEEE Transactions on Engineering Management, vol. 46, no. 2, pp. 221-229, May 1999. https://doi.org/10.1109/17.759152.

      [11] Bin Yu, Clement H. Wann, Edward D. Nowak, Kenji Noda, and Chenming Hu, “Short-channel effect improved by lateral channel- engineering in deep-sub micrometer MOSFET,†IEEE Transactions on Electron Devices, vol. 44, no. 4, pp. 42-63, April 1997.

      [12] Yuan Taur, “An analytical solution to a double-gate MOSFET with undoped body,†IEEE Electron Device Letters, vol. 21, no. 5, pp. 245- 247, May 2000. https://doi.org/10.1109/55.841310.

      [13] Yuan Taur, “Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs,†IEEE Transactions on Electron Devices, vol. 48, no. 12, pp. 2861-2869, Dec. 2001. https://doi.org/10.1109/16.974719.

      [14] Yuan Taur, Xiaoping Liang, Wei Wang, and Huaxin Lu, “A continuous, analytic drain-current model for DG MOSFETs,†IEEE Electron Device Letters, vol. 25, no. 2, pp. 107-109, Feb. 2004. https://doi.org/10.1109/LED.2003.822661.

      [15] Huaxin Lu and Yuan Taur, “An analytic potential model for symmetric and asymmetric DG MOSFETs,†IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1161-1168, May 2006. https://doi.org/10.1109/TED.2006.872093.

      [16] Benjamin Iniguez, David Jimenez, Jaume Roig, Hamdy A. Hamid, Lluis F. Marsal, and Josep Pallares, “Explicit continuous model for long-channel undoped surrounding gate MOSFETs,†IEEE Transations on Electron Devices, vol. 52, no. 8, pp. 1868-1873, Aug. 2005. https://doi.org/10.1109/TED.2005.852892.

      [17] Bo Yu, Wei Y. Lu, Huaxin Lu, and Yuan Taur, “Analytic charge model for surrounding-gate MOSFETs,†IEEE Transactions on Electron De- vices, vol. 54, no. 3, pp. 492-496, March 2007. https://doi.org/10.1109/TED.2006.890264.

      [18] Ran Yan, Abbas Ourmazd, and Kwing F. Lee, “Scaling the Si MOSFET: from bulk to SOI to bulk,†IEEE Transactions on Electron Devices, vol. 39, no. 7, pp. 1704-1710, July 1992. https://doi.org/10.1109/16.141237.

      [19] Viranjay M. Srivastava, Kalyan S. Yadav, and Ghanshyam Singh, “Explicit model of cylindrical surrounding double-gate MOSFETs,†WSEAS Transaction on Circuits and Systems, vol. 12, no. 3, pp. 81-90, March 2013.

      [20] Sourav Bairagya and Abhishek Chakraborty, “An analytical model for double surrounding gate MOSFET,†Devices for Integrated Circuit, 2017, India, 23-24 March 2017, pp. 721-725.

      [21] Viranjay M. Srivastava, “Small signal model of cylindrical surrounding double-gate MOSFET and its Parameters,†IEEE International Conference on Trends in Automation, Communications and Computing Technology, Bangalore, India, 21-22 Dec. 2015, pp. 152-156. https://doi.org/10.1109/ITACT.2015.7492672

      [22] Juan P. Duarte, Sung J. Choi, Dong Moon, Jae H. Ahn, Jee Y. Kim, Sungho Kim and Yang K. Choi, “A universal core model for multiple- gate field-effect transistors,†IEEE Transactions on Electron Devices, vol. 60, no. 2, pp. 848-855, Feb. 2013. https://doi.org/10.1109/TED.2012.2233863.

      [23] Wilfried Hansch, The drift diffusion equation and its applications in MOSFET modeling, Springer Science and Business Media, 2012.

      [24] Himangi Sood, Viranjay M. Srivastava, and Ghanshyam Singh, “Performance analysis of undoped and Gaussian doped cylindrical surrounding- gate MOSFET with its small signal modeling,†Microelectronics Journal, vol. 57, no. 1, pp. 66-75, Oct. 2016. https://doi.org/10.1016/j.mejo.2016.10.001.

      [25] Awanit Sharma and Shyam Akashe, “Performance analysis of gate-all- around field effect transistor for CMOS nanoscale devices,†International Journal of Computer Applications, vol. 84 no. 10, pp. 44-48, Dec. 2013. https://doi.org/10.5120/14616-2874.

      [26] Viranjay M. Srivastava and Ghanshyam Singh, MOSFET technologies for double-pole-four-throw radio-frequency switch, 1st Ed., Springer, Switzerland, 2014. https://doi.org/10.1007/978-3-319-01165-3.

      [27] Jean P. Colinge, Chi W. Lee, Aryan Afzalian, Nima D. Akhavan, Ran Yan, Isabelle Ferain, Pedram Razavi, Brendan O’Neill, Alan Blake, Mary White, Anne-Marie Kelleher, Brendan McCarthy and Richard Murphy, “Nanowire transistors without junctions,†Nature Nanotechnology, vol. 5, no. 10 pp. 225, Feb. 2010. https://doi.org/10.1038/nnano.2010.15.

      [28] Ming J. Chen, Wei H. Lee and Yi H. Huang, “Error-free Matthiessen’s rule in the MOSFET universal mobility region,†IEEE Transactions on Electron Devices, vol. 60, no. 2, pp. 753-758, Feb. 2013. https://doi.org/10.1109/TED.2012.2233202.

      [29] Okikioluwa E. Oyedeji and Viranjay M. Srivastava, “Carrier mobility aspects for cylindrical surrounding double-gate MOSFET,†IEEE International Conference on Engineering and Technology, India, 16-17 Dec. 2016, vol. 2, pp. 332-335.

      [30] Okikioluwa E. Oyedeji and Viranjay M. Srivastava, “Cylindrical surrounding double-gate MOSFET based amplifier: A circuit perspective,†IEEE International Conference on Intelligent Computing, Instrumentation and Control Technologies, India, 6-7 July 2017, pp. 152-155. https://doi.org/10.1109/ICICICT1.2017.8342551

      [31] Lalit Singh, Mahesh Chandra and B. P. Tyagi, "Mobility degradation and total series resistance of Cylindrical gate-all-around silicon nanowire field-effect transistor," International Journal of Engineering and Management Research, vol. 2, no. 4, pp. 5-10, Aug. 2012.

  • Downloads

  • How to Cite

    E. Oyedeji, O., & M. Srivastava, V. (2018). Effect of radius on various parameters of cylindrical surrounding double-gate (CSDG) MOSFET. International Journal of Engineering & Technology, 7(4), 2127-2131. https://doi.org/10.14419/ijet.v7i4.10110

    Received date: 2018-03-13

    Accepted date: 2018-05-23

    Published date: 2018-09-10