A novel 3-D-IC test architecture-a review

  • Authors

    • R Karthick
    • M Sundararajan
    2017-12-21
    https://doi.org/10.14419/ijet.v7i1.1.10227
  • TSV, Cross talk, integrated circuits, BIST.

  • Abstract

    Here, this paper completely examines the crosstalk noise of Through-Silicon-Vias (TSVs) in high speed operations by means of a novel 3-Dimensional-IC Test structural design. In order to decline the crosstalk, the fast rise time devices have to be circumvented except they are essential for performance in some certain circuit parts. It must be noted that this system simultaneously examines the TSVs and the memory and does not require spending additional area for a test pattern generator in case of the TSV test. With the intention of reprocessing the test patterns of new-fangled memory BIST, the value of “data†or “address†need to be fixed to some specific values. In accordance with the outcomes of the TSV grouping, here also implemented a high-efficiency, low-area-overhead TSV test structural design. The amount of test cycles essential for the purpose of finding failing TSVs and regulate the fault category effectively than that in related work.

  • References

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  • How to Cite

    Karthick, R., & Sundararajan, M. (2017). A novel 3-D-IC test architecture-a review. International Journal of Engineering & Technology, 7(1.1), 579-581. https://doi.org/10.14419/ijet.v7i1.1.10227

    Received date: 2018-03-17

    Accepted date: 2018-03-17

    Published date: 2017-12-21