Crosstalk noise minimization in novel through silicon via structures

  • Authors

    • K Nageswara Rao
    • G Veerendra Nath
    • K Hari Kishore
    2018-03-19
    https://doi.org/10.14419/ijet.v7i2.8.10325
  • Through Silicon via (TSV), Poly-Propylene Liner, Polymer Capacitance, Depletion Capacitance, Crosstalk

  • Abstract

    In recent trends, through silicon via (TSV) is essential Technologies for 3-D IC integration because of its short interconnects length and high interconnect density. Beyond the existing structure of TSV, this paper provides a novel structure to investigate the crosstalk effect and same is simulated by using a SPICE simulator and 3-D field solver. The structure of the TSV comprises of copper surrounding by insulating liner, and silicon substrate. In existing structures, silicon dioxide (Sio2) is used as insulating liner because of its material compatibility with silicon substrate. Several researches provide the problem of using Sio2 is due to its high dielectric constant; as a consequence delay will increase. Therefore, Sio2 is not appropriate for high performance applications. In this work, a novel TSV structure is reported to improve the TSV performance which uses poly-propylene polymer liner instead of oxide liner. Signal TSV is enclosed by using a poly-propylene liner and amid the analysis with doping region is created around the ground TSV. For comparison purposes, conventional and proposed TSV structures are simulated. The proposed TSV’s structure simulation results in 30% decrease in crosstalk over existing TSV structures.

  • References

    1. [1] T. Bandhopadhyay, K. J. Han, and D. Chung, “Rigorous electrical modeling of Through Silicon Vias (TSVs) with MOS capacitance effects,†IEEE Trans.Comp. Packag. Manufact. Technol., vol. 1, pp. 893–903, 2011.https://doi.org/10.1109/TCPMT.2011.2120607.

      [2] DC Yang, J. Xie, and M. Swaminathan,“A Rigorous Model for Through-Silicon Viaswith Ohmic Contact in Silicon Interposer,†IEEE microwave and wireless components letters, 2013. https://doi.org/10.1109/LMWC.2013.2270459.

      [3] Yoon, K., G. Kim, W. Lee, T. Song, and J. Kim, L.Qian, Y.xia, and G.Liang , “ Study on crosstalk characteristic of carbon nanotube through silicon vias for three dimensional integration,†in Microelectronics journal, Vol. 46, pp. 572-580, jul.2015.

      [4] C. Huang, Q. Chen, and Z. Wang, “Polymer liner formation in TSVs for 3-D integration,†IEEE Trans. Comp. Packag. Manufact.Technol., vol. 3, no. 7, July 2013.

      [5] J. Kim, J. S. Pak, and J. Cho, “High-frequency scalable electrical model and analysis of a through silicon via (TSV),†IEEE Trans. Comp. Packag. Manufact.Technol., vol. 1, no. 2, pp. 181–195, 2011.https://doi.org/10.1109/TCPMT.2010.2101890.

      [6] G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, “Electrical modeling and characterization of through silicon via for three-dimensional ICs,†IEEE Trans. Electron Devices, vol. 57, pp. 256–262, 2010.https://doi.org/10.1109/TED.2009.2034508.

      [7] X. Wang, M. Xiong, and Z. Chen, “Wideband Capacitance Evaluation of Silicon-Insulator-Silicon Through-Silicon-Vias for 3D Integration Applications,†IEEE Electron Device Letters, vol. 37, no. 2, Feb. 2016. https://doi.org/10.1109/LED.2015.2506551.

      [8] A. E. Engin and N. S. Raghavan, “Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design,†in Proc. IEEE Int. 3D Syst. Integr. Conf., Japan, pp. 1–4, 2012.https://doi.org/10.1109/3DIC.2012.6263049.

      [9] G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, “ Electrical modeling and characterization of through silicon via for three-dimensional ICs,†IEEE Trans. Electron Devices, Vol. 57, no. 1, pp. 256-262, Jan. 2010.https://doi.org/10.1109/TED.2009.2034508.

      [10] Dr. Seetaiah Kilaru, Hari Kishore K, Sravani T, Anvesh Chowdary L, Balaji T “Review and Analysis of Promising Technologies with Respect to fifth Generation Networksâ€, 2014 First International Conference on Networks & Soft Computing, ISSN:978-1-4799-3486-7/14,pp.270-273,August2014.

      [11] Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing Using BIST Designs†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.12, Issue No.3, page: 636-643, April 2017.

      [12] P Bala Gopal, K Hari Kishore, B.PraveenKittu “An FPGA Implementation of On Chip UART Testing with BIST Techniquesâ€, International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, Number 14 , pp. 34047-34051, August 2015.

      [13] A Murali, K Hari Kishore, D Venkat Reddy "Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.11, Issue No.12, page: 2643-2650, December 2016.

      [14] Mahesh Mudavath, K Hari Kishore, D Venkat Reddy "Design of CMOS RF Front-End of Low Noise Amplifier for LTE System Applications Integrating FPGAs†Asian Journal of Information Technology, ISSN No: 1682-3915, Vol No.15, Issue No.20, page: 4040-4047, December 2016.

      [15] N Bala Dastagiri, K Hari Kishore "Novel Design of Low Power Latch Comparator in 45nm for Cardiac Signal Monitoringâ€, International Journal of Control Theory and Applications, ISSN No: 0974-5572, Vol No.9, Issue No.49, page: 117-123, May 2016.

      [16] N Bala Gopal, Kakarla Hari Kishore "Reduction of Kickback Noise in Latched Comparators for Cardiac IMDs†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.43, Page: 1-6, November 2016.

      [17] S Nazeer Hussain, K Hari Kishore "Computational Optimization of Placement and Routing using Genetic Algorithm†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.47, page: 1-4, December 2016.

      [18] N.Prathima, K.Hari Kishore, “Design of a Low Power and High Performance Digital Multiplier Using a Novel 8T Adderâ€, International Journal of Engineering Research and Applications, ISSN: 2248-9622, Vol. 3, Issue.1, Jan-Feb., 2013.

      [19] Harikishore Kakarla, Madhavi Latha M and Habibulla Khan, “Transition Optimization in Fault Free Memory Application Using Bus-Align Modeâ€, European Journal of Scientific Research, Vol.112, No.2, pp.237-245, ISSN: 1450-216x135/1450-202x, October 2013.

      [20] SHAIK.RAZIA, M.R.NARASINGARAO published “Machine learning techniques for thyroid disease diagnosis - A review†in Scopus Indexed Journal INDJST (Indian Journal of Science and Technology, ISSN: 09746846, volume-9, Issue 28, July 2016, Article number 93705).

      [21] SHAIK.RAZIA, M.R.NARASINGARAO published “A Neuro computing frame work for thyroid disease diagnosis using machine learning techniques†in Scopus Indexed Journal JATIT (Journal of Theoretical and Applied Information Technology, 15th May 2017. Vol.95. No.9. Pages 1996-2005) ISSN: 1992-8645 www.jatit.org E-ISSN: 1817-3195.

      [22] T. Padmapriya and V. Saminadan, “Distributed Load Balancing for Multiuser Multi-class Traffic in MIMO LTE-Advanced Networksâ€, Research Journal of Applied Sciences, Engineering and Technology (RJASET) - Maxwell Scientific Organization, ISSN: 2040-7459; e-ISSN: 2040-7467, vol.12, no.8, pp: 813-822, April 2016.

      [23] S.V.Manikanthan and K.Baskaran “Low Cost VLSI Design Implementation of Sorting Network for ACSFD in Wireless Sensor Networkâ€, CiiT International Journal of Programmable Device Circuits and Systems,Print: ISSN 0974 – 973X & Online: ISSN 0974 – 9624, Issue : November 2011, PDCS112011008.

  • Downloads

  • How to Cite

    Nageswara Rao, K., Veerendra Nath, G., & Hari Kishore, K. (2018). Crosstalk noise minimization in novel through silicon via structures. International Journal of Engineering & Technology, 7(2.8), 56-62. https://doi.org/10.14419/ijet.v7i2.8.10325

    Received date: 2018-03-19

    Accepted date: 2018-03-19

    Published date: 2018-03-19