Design of voltage level shifter for power-efficient applications using 45nm technology

  • Authors

    • P Sahithi
    • K Hari Kishore
    • E Raghuveera
    • P Gopi Krishna
    2018-03-19
    https://doi.org/10.14419/ijet.v7i2.8.10339
  • Conventional Level Shifter, Dynamic Level Shifter, Leakage Voltage, Level Shifter with Wilson Current Mirror, 45nm Technology, Voltage, Power Consumption, Gain and Gain Bandwidth Product (GBW).

  • Abstract

    The paper describes a voltage level shifter for power efficient applications which is simulated in tanner spice tool using 45nm technology. The conservative voltage level shifter is designed by using 6 transistors. The voltage level shifter cell generally used for shifting the voltage range of the signal from one voltage domain to another. This is required when the chip operate at multiple voltage domains. The circuit parameters like leakage voltage and average power dissipation are calculate for this circuit. Mainly level shifter consists of two voltage levels. One is low logic supply voltage (VDDL) another one is high logic supply voltage (VDDH). The simulation results of proposed level shifter with Wilson current mirror by 45nm technology for the input frequency of 1MHZ, the power dissipation of 0.177nW with 3db gain of 9.78.

  • References

    1. [1] Seyed Rasool Hosseini, Mehdi Saberi, and Reza Lotfi “A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications†Year: 2017, Volume:25, Issue:3.

      [2] Devesh Dwivedi, Suman Dwivedi, EswararaoPotladhurthi†Voltage up level shifter with improved performance and reduced power†2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)Year: 2012.

      [3] KamniPatkar, ShyamAkasheâ€Design of Level Shifter for Low Power Applicationsâ€2016 Symposium on Colossal Data Analysis and Networking (CDAN) Year: 2016https://doi.org/10.1109/CDAN.2016.7570905.

      [4] K. Usami et al., “Automated low-power technique exploiting multiple supply voltages applied to a media processor,†IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 463–472, Mar. 1998.https://doi.org/10.1109/4.661212.

      [5] S. R. Hosseini, M. Saberi, and R. Lotfi, “A low-power subthreshold to above-threshold voltage level shifter,†IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 10, pp. 753–757, Oct. 2014.

      [6] T.-H. Chen, J. Chen, and L. T. Clark, “Subthreshold to above threshold level shifter design,†J. Low Power Electron., vol. 2, no. 2, pp. 251–258, Aug. 2006.https://doi.org/10.1166/jolpe.2006.071.

      [7] A. Hasanbegovic and S. Aunet, “Low-power subthreshold to above threshold level shifter in 90 nm process,†in Proc. NORCHIP Conf., Nov. 16–17, 2009, pp 1–4. https://doi.org/10.1109/NORCHP.2009.5397793.

      [8] A. P. Chandrakasanet.al., (1995) “Minimizing power consumption in digital CMOS circuits,†Proceedings of the IEEE, vol.83, no.4, pp.498-523.https://doi.org/10.1109/5.371964.

      [9] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen,(1992) “Low- power CMOS digital design,â€IEEE J. Solid-State Circuits, vol. 27,no.4, pp. 473–484.https://doi.org/10.1109/4.126534.

      [10] Dr. Seetaiah Kilaru, Hari Kishore K, Sravani T, Anvesh Chowdary L, Balaji T “Review and Analysis of Promising Technologies with Respect to fifth Generation Networksâ€, 2014 First International Conference on Networks & Soft Computing, ISSN:978-1-4799-3486-7/14,pp.270-273,August2014.

      [11] Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing Using BIST Designs†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.12, Issue No.3, page: 636-643, April 2017.

      [12] P Bala Gopal,K Hari Kishore, B.PraveenKittu “An FPGA Implementation of On Chip UART Testing with BIST Techniquesâ€, International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, Number 14 , pp. 34047-34051, August 2015.

      [13] A. Murali, K Hari Kishore, D Venkat Reddy "Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.11, Issue No.12, page: 2643-2650, December 2016.

      [14] Mahesh Mudavath, K Hari Kishore, D Venkat Reddy "Design of CMOS RF Front-End of Low Noise Amplifier for LTE System Applications Integrating FPGAs†Asian Journal of Information Technology, ISSN No: 1682-3915, Vol No.15, Issue No.20, page: 4040-4047, December 2016.

      [15] N Bala Dastagiri, K Hari Kishore "Novel Design of Low Power Latch Comparator in 45nm for Cardiac Signal Monitoringâ€, International Journal of Control Theory and Applications, ISSN No: 0974-5572, Vol No.9, Issue No.49, page: 117-123, May 2016..

      [16] N Bala Gopal, Kakarla Hari Kishore "Reduction of Kickback Noise in Latched Comparators for Cardiac IMDs†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.43, Page: 1-6, November 2016.

      [17] S Nazeer Hussain, K Hari Kishore "Computational Optimization of Placement and Routing using Genetic Algorithm†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.47, page: 1-4, December 2016.

      [18] N.Prathima, K.Hari Kishore, “Design of a Low Power and High Performance Digital Multiplier Using a Novel 8T Adderâ€, International Journal of Engineering Research and Applications, ISSN: 2248-9622, Vol. 3, Issue.1, Jan-Feb., 2013.

      [19] Harikishore Kakarla, Madhavi Latha M and Habibulla Khan, “Transition Optimization in Fault Free Memory Application Using Bus-Align Modeâ€, European Journal of Scientific Research, Vol.112, No.2, pp.237-245,ISSN: 1450-216x135/1450-202x, October 2013.

      [20] Shaik.Razia, M.R.Narasingarao published “Machine learning techniques for thyroid disease diagnosis - A review†Indian Journal of Science and Technology, ISSN: 09746846, volume-9, Issue 28, July 2016.

      [21] Shaik.Razia, M.R.Narasingarao published “A Neuro computing frame work for thyroid disease diagnosis using machine learning techniques†Journal of Theoretical and Applied Information Technology, 15th May 2017. Vol.95. No.9. Pages 1996-2005) ISSN: 1992-8645.

      [22] T.Padmapriya and V.Saminadan, “Utility based Vertical Handoff Decision Model for LTE-A networksâ€, International Journal of Computer Science and Information Security, ISSN 1947-5500, vol.14, no.11, November 2016.

      [23] S.V.Manikanthan and D.Sugandhi“Interference Alignment Techniques For Mimo Multicell Based On Relay Interference Broadcast Channel†International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE) ISSN: 0976-1353 Volume- 7, Issue 1 –MARCH 2014.

  • Downloads

  • How to Cite

    Sahithi, P., Hari Kishore, K., Raghuveera, E., & Gopi Krishna, P. (2018). Design of voltage level shifter for power-efficient applications using 45nm technology. International Journal of Engineering & Technology, 7(2.8), 103-108. https://doi.org/10.14419/ijet.v7i2.8.10339

    Received date: 2018-03-19

    Accepted date: 2018-03-19

    Published date: 2018-03-19