Efficient high throughput decoding architecture for non-binary LDPC codes

  • Authors

    • C Arul Murugan
    • B Banuselvasaraswathy
    • K Gayathree
    • M Ishwarya Niranjana
    2018-03-19
    https://doi.org/10.14419/ijet.v7i2.8.10407
  • .

  • Abstract

    This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz.

  • References

    1. [1] Injae Yoo and In-Cheol Park, “Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks,†IEEE Transactions on Circuits and Systems II, Volume: 64, Issue: 9, pp 1057 – 1061, Sept. 2017.

      [2] Jian Wang, Kangli Zhang and Harald Kröll, “Design of QPP Interleavers for the Parallel Turbo Decoding Architecture,†IEEE Transactions on Circuits and Systems I: Regular Papers,Volume: 63, Issue: 2, pp. 288-299, Feb. 2016.

      [3] B. Banuselvasaraswathy, “Trellis based decoding architecture for non-binary LDPC codes using modified Fano algorithm to achieve high throughputâ€, International Journal of Advanced Information Science and Technology (IJAIST),Vol.23, No.23, pp 383-389, March 2014.

      [4] B. Banuselvasaraswathy, “A New Enhanced Trellis Based Decoding Architecture for Punctured Codes using Modified Max Product Algorithmâ€, International Journal of Advanced Information Science and Technology (IJAIST), Vol.18, No.18, pp 36-43,October 2013.

      [5] Yeong-Luh Ueng, Kuo-Hsuan Liao, Hsueh-Chih Chou, and Chung-Jay Yang, “A High-Throughput Trellis-Based Layered Decoding Architecture for Non-Binary LDPC Codes Using Max-Log-QSPAâ€, IEEE Transactions on Signal Processing,Vol.61,No.11,pp 2940 – 2950, June,2013.

      [6] M. C. Davey and D. J. C. MacKay, “Low-density parity check codes over GF (q),†IEEE Commun. Lett, vol. 2, no. 6, pp. 165–167, Jun. 1998.

      [7] H. Wymeersch, H. Steendam and M. Moeneclaey, “Log-domain decoding of LDPC codes over GF(q),â€in Proc .IEEE Int. Conf. Commun. (ICC), Paris, France, Jun. 20–24, 2004, pp. 772–77

      [8] L.Barnault and D.Declercq, “Fast decoding algorithm for LDPC over GF(2n)â€, in Proc. IEEE Inf. Theory Workshop (ITW), Paris, France, Mar. 31–Apr. 4, 2003, pp. 70–73.

      [9] H.Songand, J.R.Cruz, “Reduced complexity decoding of Q-ary LDPC codes for magnetic recording,â€IEEETrans.Magn.,vol.39,no.2,pp. 1081–1087, Mar. 2003.

      [10] D. Declercq and M. Fossorier, “Decoding algorithms for nonbinary LDPC codes over GF (q),†IEEE Trans. Commun., vol. 55, no. 4, pp. 633–643, Apr. 2007.

      [11] V. Savin, “Min-max decoding for non-binary LDPC codes,†in Proc. IEEE Int. Symp. Inf. Theory (ISIT), Toronto, ON, Canada, Jul. 6–11, 2008, pp. 960–964.

      [12] A.C.Spagnol, E.Popovici,andW.Marnane,“Hardware implementation of LDPC decoders,†IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 12, pp. 2609–2620, Dec. 2009.

      [13] A. Voicila, D. Declereq, F. Verdier, M. Fossorier, and P. Urard, “Low complexity low-memory EMS algorithm for non-binary LDPC codes,†in Proc. IEEE Int.Conf.Commun.,Jun.2007,pp.671–676

      [14] J. Lin, J. Sha, Z. Wang, and L. Li, “Efï¬cient decoder design for nonbinary quasicyclic LDPC codes,†IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 5, pp. 1071–1082, May 2010.

      [15] C. Zhang and K. K. Parhi, “A network-efï¬cient nonbinary QC-LDPC decoder architecture,†IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 6, pp. 1359–1371, Jun. 2012.

      [16] X. Zhang and F. Cai, “Reduced-complexity decoder architecture for non-binary LDPC codes, â€IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 10, no. 7, pp. 1229–1238, Jul. 2011.

      [17] Y.-L. Ueng, C.-Y. Leong, C.-J. Yang, C.-C. Cheng, K.-H. Liao, and S.-W.Chen, “An efï¬cient layered decoding architecture for non-binary QC-LDPC codes,†IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, pp. 385–398, Feb. 2012.

      [18] X. Zhang, F. Cai, and S. Lin, “Low-complexity reliability-based message passing decoder architectures for non-binary LDPC codes,†IEEE Trans.VLSI Syst., vol.20, no.11, pp.1938–1950, Nov.2012.

      [19] C.-Y.Chen, Q.Huang, C.-C. Chao and S.Lin, “Two low-complexity reliability-based message-passing algorithms for decoding non-binary LDPC codes,†IEEE Trans. Commun., vol.58, no.11, pp.3140–3147, Nov. 2010.

      [20] R. Kalaivani, K. Ramash Kumar, S. Jeevananthan, “Implementation of VSBSMC plus PDIC for Fundamental Positive Output Super Lift-Luo Converter,†Journal of Electrical Engineering, Vol. 16, Edition: 4, 2016, pp. 243-258.

      [21] K. Ramash Kumar,â€Implementation of Sliding Mode Controller plus Proportional Integral Controller for Negative Output Elementary Boost Converter,†Alexandria Engineering Journal (Elsevier), 2016, Vol. 55, No. 2, pp. 1429-1445.

      [22] P. Sivakumar, V. Rajasekaran, K. Ramash Kumar, “Investigation of Intelligent Controllers for Varibale Speeed PFC Buck-Boost Rectifier Fed BLDC Motor Drive,†Journal of Electrical Engineering (Romania), Vol.17, No.4, 2017, pp. 459-471.

      [23] K. Ramash Kumar, D.Kalyankumar, DR.V.Kirbakaran†An Hybrid Multi level Inverter Based DSTATCOM Control, Majlesi Journal of Electrical Engineering, Vol. 5. No. 2, pp. 17-22, June 2011, ISSN: 0000-0388.

      [24] K. Ramash Kumar, S. Jeevananthan, “A Sliding Mode Control for Positive Output Elementary Luo Converter,†Journal of Electrical Engineering, Volume 10/4, December 2010, pp. 115-127.

      [25] K. Ramash Kumar, Dr.S. Jeevananthan,†Design of a Hybrid Posicast Control for a DC-DC Boost Converter Operated in Continuous Conduction Mode†(IEEE-conference PROCEEDINGS OF ICETECT 2011), pp-240-248, 978-1-4244-7925-2/11.

      [26] K. Ramash Kumar, Dr. S. Jeevananthan,†Design of Sliding Mode Control for Negative Output Elementary Super Lift Luo Converter Operated in Continuous Conduction Modeâ€, (IEEE conference Proceeding of ICCCCT-2010), pp. 138-148, 978-1-4244-7768-5/10.

      [27] K. Ramash Kumar, S. Jeevananthan, S. Ramamurthy†Improved Performance of the Positive Output Elementary Split Inductor-Type Boost Converter using Sliding Mode Controller plus Fuzzy Logic Controller, WSEAS TRANSACTIONS on SYSTEMS and CONTROL, Volume 9, 2014, pp. 215-228.

      [28] N. Arunkumar, T.S. Sivakumaran, K. Ramash Kumar, S. Saranya, â€Reduced Order Linear Quadratic Regulator plus Proportional Double Integral Based Controller for a Positive Output Elementary Super Lift Luo-Converter,†JOURNAL OF THEORETICAL AND APPLIED INFORMATION TECHNOLOGY, July 2014. Vol. 65 No.3, pp. 890-901.

      [29] Arunkumar, T.S. Sivakumaran, K. Ramash Kumar, “Improved Performance of Linear Quadratic Regulator plus Fuzzy Logic Controller for Positive Output Super Lift Luo-Converter,†Journal of Electrical Engineering, Vol. 16, Edition:3, 2016, pp. 397-408.

      [30] S.V.Manikanthan and K.Baskaran “Low Cost VLSI Design Implementation of Sorting Network for ACSFD in Wireless Sensor Networkâ€, CiiT International Journal of Programmable Device Circuits and Systems,Print: ISSN 0974 – 973X & Online: ISSN 0974 – 9624, Issue : November 2011, PDCS112011008.

      [31] S.V.Manikanthan and V.Rama“Optimal Performance Of Key Predistribution Protocol In Wireless Sensor Networks†International Innovative Research Journal of Engineering and Technology, ISSN NO: 2456-1983, Vol-2,Issue –Special –March 2017.

      [32] T. Padmapriya and V.Saminadan, “Handoff Decision for Multi-user Multiclass Traffic in MIMO-LTE-A Networksâ€, 2nd International Conference on Intelligent Computing, Communication & Convergence (ICCC-2016) – Elsevier - PROCEDIA OF COMPUTER SCIENCE, vol. 92, pp: 410-417, August 2016.

      [33] P. SIVA SANKAR, “A Secure and Fast Authentication implementation between the Entities using Trust Aware Algorithmâ€, International Innovative Research Journal of Engineering and Technology. September 2016 Volume 2 Issue No: 1. 34-40.

      [34] R. Kalaivani, K. Ramash Kumar, S. Jeevananthan, “Implementation of VSBSMC plus PDIC for Fundamental Positive Output Super Lift-Luo Converter,†Journal of Electrical Engineering, Vol. 16, Edition: 4, 2016, pp. 243-258.

  • Downloads

  • How to Cite

    Arul Murugan, C., Banuselvasaraswathy, B., Gayathree, K., & Ishwarya Niranjana, M. (2018). Efficient high throughput decoding architecture for non-binary LDPC codes. International Journal of Engineering & Technology, 7(2.8), 195-200. https://doi.org/10.14419/ijet.v7i2.8.10407

    Received date: 2018-03-21

    Accepted date: 2018-03-21

    Published date: 2018-03-19