Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology

  • Authors

    • K Hari Kishore
    • K DurgaKoteswara Rao
    • G Manvith
    • K Biswanth
    • P Alekhya
    2018-03-19
    https://doi.org/10.14419/ijet.v7i2.8.10413
  • GDI(Gate Diffusion Input), Modified or Updated GDI technique, Magnitude Comparator,

  • Abstract

    Of late, low power configuration took shape into the mostimportant concentrations in designing the latest VLSI circuits. By considering the same at the maximum priority, another outline of two-bit GDI based Magnitude or Digital Comparator are recommended and actualized with the assistance of Modified GDI transistors. Comparators are building blocks in advanced VLSI configuration circuits. In the current patterns the necessity for occupying less area in chip and low power compact devices. In this paper we introduced another Magnitude Comparator which willutilize low power, and gives a quick results and occupying less chip area in Modified GDI technology. The modified GDI procedure dependent extent comparator has favorable position of less control utilization as for different outline parameters; few on-chip zones secured as small number of transistors are utilized in circuit configuration when related with traditional CMOS size comparator. Either of the circuits is outlined and executed utilizing Tanner EDA Tool version 16.0 at 180nm processing technologies.

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  • How to Cite

    Hari Kishore, K., DurgaKoteswara Rao, K., Manvith, G., Biswanth, K., & Alekhya, P. (2018). Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology. International Journal of Engineering & Technology, 7(2.8), 222-226. https://doi.org/10.14419/ijet.v7i2.8.10413

    Received date: 2018-03-21

    Accepted date: 2018-03-21

    Published date: 2018-03-19