Design and comparative analysis of inexact speculative adder and multiplier
-
2018-03-19 https://doi.org/10.14419/ijet.v7i2.8.10472 -
Inexact Speculative Adder, Multiplier, Carry Look Ahead Adder, Pipelining, Delay. -
Abstract
A Carry look ahead adder is a sort of the summer used in the logic design of the digital systems. The CLA boost up the speed by decreasing the measure of duration needed to calculate the carry bits. The CLA based outline of the inexact speculative adder is pipelined architecture to incorporate couple of logic paths along its basic way and in this manner, improving the recurrence of operation. This paper presents the comparative analysis of the pipelined inexact speculative adder and the general carry look ahead adder and showed that the delay is reduced to 48.27% when compared to carry look ahead adder and also we have designed the pipelined multiplier using the Inexact speculative adders and observed that the delay  is reduced to 48.32% when compared to the normal multiplier. This entail Xilinx ISE Design Suite 14.5 Tool.
-
References
[1] Vincent Camus, Jeremy Schlachter, Christian Enz â€Energy- Efï¬cient Inexact Speculative Adder with High Performance and Accuracy Control†in Circuits and Systems (ISCAS) IEEE International Symposium on ,May 2015 pp.45-48.
[2] Ing-Chao Lin, Yi-Ming Yang, Cheng-ChianLinâ€high performance low power carry speculative addewith VARIABLE LATENCY†in IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume: 23, Issue: 9, Sept. 2015.
[3] Y. PRUDHVIBHASKAR,S K AHEMED ALI, B V PAVAN KUMAR “PERFORMANCE IMPROVEMENT AND AREA OPTIMIZATION OF CARRY SPECULATIVE ADDITION USING MODIFIED CARRY GENERATORS†in International Journal of Scientific Research Engineering & Technology (IJSRET) Volume 5, Issue 2, February 2016.
[4] Rahul Shrestha “High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder†in VLSI Design, Automation and Test (VLSI-DAT), 2017 International Symposium on April 2017.
[5] Alessandro Cilardo, DavideDeCar, NicolaPetr, Francesco Caserta, Nicola Mazzocca, Ettore Napoli, Antonio Giuseppe Maria Strollo†High Speed Speculative Multipliers Based on Speculative Carry-Save Tree†in IEEE Transactions on Circuits and Systems I: Regular PapersVolume: 61, Issue: 12, Dec. 2014
[6] Anju Sunny, Binu K. Mathew†Design of High Speed Approximate Multiplier with Carry Speculation Compressor†in IJSTE - International Journal of Science Technology &Engineering, Volume 2, Issue4, October 2015.
[7] Alfiya V M, Meera Thampy†High Speed Speculative Multiplier Using 3 Step Speculative Carry Save Reduction Tree†in IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) p- ISSN: 2278-8735. PP 65-72.
[8] Dr. Seetaiah Kilaru, Hari Kishore K, Sravani T, Anvesh Chowdary L, Balaji T “Review and Analysis of Promising Technologies with Respect to fifth Generation Networksâ€, 2014 First International Conference on Networks & Soft Computing,ISSN:978-1-4799-3486-7/14,pp.270-273,August2014.
[9] Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing Using BIST Designs†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.12, Issue No.3, page: 636-643, April 2017.
[10] P Bala Gopal, K Hari Kishore, R.R Kalyan Venkatesh, P Harinath Mandalapu“An FPGA Implementation of On Chip UART Testing with BIST Techniquesâ€, International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, Number 14 , pp. 34047-34051, August 2015
[11] A Murali, K Hari Kishore, D Venkat Reddy "Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.11, Issue No.12, page: 2643-2650, December 2016.
[12] Mahesh Mudavath, K Hari Kishore, D Venkat Reddy "Design of CMOS RF Front-End of Low Noise Amplifier for LTE System Applications Integrating FPGAs†Asian Journal of Information Technology, ISSN No: 1682-3915, Vol No.15, Issue No.20, page: 4040-4047, December 2016.
[13] N Bala Dastagiri, Kakarla Hari Kishore "Reduction of Kickback Noise in Latched Comparators for Cardiac IMDs†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.43, Page: 1-6, November 2016.
[14] S Nazeer Hussain, K Hari Kishore "Computational Optimization of Placement and Routing using Genetic Algorithm†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.47, page: 1-4, December 2016.
[15] Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing Using BIST Designs†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.12, Issue No.3, page: 636-643, April 2017.
[16] N Bala Dastagiri,, K Hari Kishore "Analysis of Low Power Low Kickback Noise in Dynamic Comparators in Pacemakers†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.44, page: 1-4, November 2016.
[17] P Ramakrishna, K. Hari Kishore, “Design of Low Power 10GS/s 6-Bit DAC using CMOS Technology “International Journal of Engineering and Technology , ISSN No: 2227-524X, Vol No: 7, Issue No: 1.5, Page No: 226-229, January 2018.
[18] A Murali, K. Hari Kishore, “Efficient and High Speed Key Independent AES Based Authenticated Encryption Architecture using FPGAs “International Journal of Engineering and Technology, ISSN No: 2227-524X, Vol No: 7, Issue No: 1.5, Page No: 230-233, January 2018.
[19] Y Avinash, K Hari Kishore ‘’Designing Asynchronous FIFO for Low Power DFT Implementation’’ International Journal of Pure and Applied Mathematics, ISSN No: 1314-3395, Vol No: 115, Issue No: 8, Page No: 561-566, September 2017.
[20] G.S.Spandana,K Hari Kishore “A Contemporary Approach For Fault Diagnosis In Testable Reversible Circuits By Employing The Cnt Gate Libraryâ€International Journal of Pure and Applied Mathematics, ISSN No: 1314-3395, Vol No: 115, Issue No: 7, Page No: 537-542, September 2017.
[21] K.Hari Kishore, P. Sri Vidhya, A. Bhavana, O. Venkata Krishna "Comparison of Power Dissipation of ALU by using Different Technologies†International Journal of Pure and Applied Mathematics, ISSN No: 1314-3395, Vol No: 115, Issue No: 7, Page No: 399-403, September 2017.
[22] Avinash Yadlapati, Dr. Hari Kishore Kakarla, “An Advanced AXI Protocol Verification using Verilog HDLâ€, Wulfenia Journal, ISSN: 1561-882X, Volume 22, No: 4, pp. 307-314, April2015.
[23] T. Padmapriya and V. Saminadan, “Inter-cell Load Balancing technique for multi-class traffic in MIMO-LTE-A Networksâ€, International Journal of Electrical, Electronics and Data Communication (IJEEDC), ISSN: 2320- 2084, vol.3, no.8, pp. 22-26, Aug 2015.
[24] S.V.Manikanthan and K.Baskaran “Low Cost VLSI Design Implementation of Sorting Network for ACSFD in Wireless Sensor Networkâ€, CiiT International Journal of Programmable Device Circuits and Systems,Print: ISSN 0974 – 973X & Online: ISSN 0974 – 9624, Issue : November 2011, PDCS112011008.
[25] R. Kalaivani, K. Ramash Kumar, S. Jeevananthan, “Implementation of VSBSMC plus PDIC for Fundamental Positive Output Super Lift-Luo Converter,†Journal of Electrical Engineering, Vol. 16, Edition: 4, 2016, pp. 243-258.
-
Downloads
-
How to Cite
Hari Kishore, K., K. V.Prasad, B., Manoj Sai Teja, Y., Akhila, D., Nikhil Sai, K., & Sravan Kumar, P. (2018). Design and comparative analysis of inexact speculative adder and multiplier. International Journal of Engineering & Technology, 7(2.8), 413-418. https://doi.org/10.14419/ijet.v7i2.8.10472Received date: 2018-03-22
Accepted date: 2018-03-22
Published date: 2018-03-19