The reordered deblocking filter and SAO architecture for HEVC system

  • Authors

    • N Nandhagopal
    • S Navaneethan
    • C Arul Murugan
    2018-03-19
    https://doi.org/10.14419/ijet.v7i2.8.10544
  • HEVC, SAO, H.264/AV

  • High Efficiency Video Coding (HEVC) used in broad band and wireless applications employs two in-loop filters to remove the blurring artifacts, blocking artifacts and ringing artifacts. The standard h.264/AVC deblocking filter which requires more memory initially filters the horizontal borders, followed by the vertical borders. The results of vertical borders filtering are utilized in the horizontal filtering process and the obtained results are further stored in temporary memory. The proposed system comprises of a reordering filter to reduce the order of the filter and a SAO to modify the decoded samples to a new offset value inorder to perform robust encryption mechanism. Hence reorder filter reduces the memory needed for this filtering process. In HEVC, SAO is an in-loop filter and located next to deblocking filter. The idea of SAO is to compensate renovated samples by adding an offset to each pixel, so that the distortion between renovated picture and original one can be reduced. Implementation of proposed simulation work is done by Verilog HDL and implemented using Virtex 6 FPGA to compute the power and hardware requirements in terms of LUT and slice registers.

  • References

    1. [1] S.Srinivasan, “Windows Media Video 9: Overview and applications,†Signal Process. Image Communcation., vol. 19,no. 9, pp. 851–875, Oct. 2004.

      [2] C.-M. Fu, CE13: „Sample Adaptive Offset with LCU-Independent Decodingâ€, JCTVC-E049, Mar. 2011.

      [3] Yang Zhang, Zhi Liu, Jianfeng Qu : “Sample Adaptive Offset Optimization in HEVC†, Sensors & Transducers, Vol 182, Issue11,Nov.2014, pp. 237-243

      [4] Norkin, A., Bjontegaard, G., Fuldseth, M., Ikeda, M., Andersson, K., Zhou, M. and Van der Auwera, G., 2012. HEVC deblocking filter. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), pp.1746-1754.

      [5] Esche, M., Glantz, A., Krutz, A. and Sikora, T., 2012. Adaptive temporal trajectory filtering for video compression. IEEE Transactions on Circuits and Systems for Video Technology, 22(5), pp.659-670.

      [6] Ozcan, E., Adibelli, Y. and Hamzaoglu, I., 2013. A high performance deblocking filter hardware for high efficiency video coding. IEEE Transactions on Consumer Electronics, 59(3), pp.714-720.

      [7] Vanne, J., Viitanen, M., Hamalainen, T.D. and Hallapuro, A., 2012. Comparative rate-distortion-complexity analysis of HEVC and AVC video codecs. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), pp.1885-1898.

      [8] Description of Core Experiment 1 (CE1): Sample Adaptive Offset Filtering, JCTVC-H1101, eb. 2012.

      [9] R. Song, H. Cui, Y. Li, and X. Song, “A five-stage pipeline design of binary arithmetic encoder in H.264/AVC,†in Proc. Asia-Pacific Signal Inform. Process. Assoc. Annu. Summit Conf., Dec. 2012, pp. 1–4.

      [10] V. Rosa, L. Max, and S. Bampi, “High performance architectures for the arithmetic encoder of the H.264/AVC CABAC entropy coder,†in Proc. IEEE 17th Int. Conf. Electron., Circuits, Syst., Dec. 2010, pp. 383–386.

      [11] R. Kalaivani, K. Ramash Kumar, S. Jeevananthan, “Implementation of VSBSMC plus PDIC for Fundamental Positive Output Super Lift-Luo Converter,†Journal of Electrical Engineering, Vol. 16, Edition: 4, 2016, pp. 243-258.

      [12] K. Ramash Kumar,â€Implementation of Sliding Mode Controller plus Proportional Integral Controller for Negative Output Elementary Boost Converter,†Alexandria Engineering Journal (Elsevier), 2016, Vol. 55, No. 2, pp. 1429-1445.

      [13] P. Sivakumar, V. Rajasekaran, K. Ramash Kumar, “Investigation of Intelligent Controllers for Varibale Speeed PFC Buck-Boost Rectifier Fed BLDC Motor Drive,†Journal of Electrical Engineering (Romania), Vol.17, No.4, 2017, pp. 459-471.

      [14] K. Ramash Kumar, D.Kalyankumar, DR.V.Kirbakaran†An Hybrid Multi level Inverter Based DSTATCOM Control, Majlesi Journal of Electrical Engineering, Vol. 5. No. 2, pp. 17-22, June 2011, ISSN: 0000-0388.

      [15] K. Ramash Kumar, S. Jeevananthan, “A Sliding Mode Control for Positive Output Elementary Luo Converter,†Journal of Electrical Engineering, Volume 10/4, December 2010, pp. 115-127.

      [16] K. Ramash Kumar, Dr.S. Jeevananthan,†Design of a Hybrid Posicast Control for a DC-DC Boost Converter Operated in Continuous Conduction Mode†(IEEE-conference PROCEEDINGS OF ICETECT 2011), pp-240-248, 978-1-4244-7925-2/11.

      [17] K. Ramash Kumar, Dr. S. Jeevananthan,†Design of Sliding Mode Control for Negative Output Elementary Super Lift Luo Converter Operated in Continuous Conduction Modeâ€, (IEEE conference Proceeding of ICCCCT-2010), pp. 138-148, 978-1-4244-7768-5/10.

      [18] K. Ramash Kumar, S. Jeevananthan, S. Ramamurthy†Improved Performance of the Positive Output Elementary Split Inductor-Type Boost Converter using Sliding Mode Controller plus Fuzzy Logic Controller, WSEAS TRANSACTIONS on SYSTEMS and CONTROL, Volume 9, 2014, pp. 215-228.

      [19] N. Arunkumar, T.S. Sivakumaran, K. Ramash Kumar, S. Saranya, â€Reduced Order Linear Quadratic Regulator plus Proportional Double Integral Based Controller for a Positive Output Elementary Super Lift Luo-Converter,†JOURNAL OF THEORETICAL AND APPLIED INFORMATION TECHNOLOGY, July 2014. Vol. 65 No.3, pp. 890-901.

      [20] Arunkumar, T.S. Sivakumaran, K. Ramash Kumar, “Improved Performance of Linear Quadratic Regulator plus Fuzzy Logic Controller for Positive Output Super Lift Luo-Converter,†Journal of Electrical Engineering, Vol. 16, Edition:3, 2016, pp. 397-408.

      [21] S.V.Manikanthan and K.Baskaran “Low Cost VLSI Design Implementation of Sorting Network for ACSFD in Wireless Sensor Networkâ€, CiiT International Journal of Programmable Device Circuits and Systems,Print: ISSN 0974 – 973X & Online: ISSN 0974 – 9624, Issue : November 2011, PDCS112011008.

      [22] T. Padmapriya and V. Saminadan, “Distributed Load Balancing for Multiuser Multi-class Traffic in MIMO LTE-Advanced Networksâ€, Research Journal of Applied Sciences, Engineering and Technology (RJASET) - Maxwell Scientific Organization , ISSN: 2040-7459; e-ISSN: 2040-7467, vol.12, no.8, pp:813-822, April 2016.

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    Nandhagopal, N., Navaneethan, S., & Arul Murugan, C. (2018). The reordered deblocking filter and SAO architecture for HEVC system. International Journal of Engineering & Technology, 7(2.8), 617-621. https://doi.org/10.14419/ijet.v7i2.8.10544