Implementation of modified Feistel block cipher for OTP generation using Verilog HDL

  • Authors

    • Fazal Noorbasha
    • K Hari Kishore
    • T. Naveen
    • A. Sai Anusha
    • Y. Manisha
    • K. Revathi
    • M. Manasa
    2018-03-19
    https://doi.org/10.14419/ijet.v7i2.8.10678
  • Feistel Cipher, OTP, Symmetric-keys, Field Programmable Gate Array (FPGA), Verilog HDL.

  • Abstract

    In this paper we modified feistel block cipher to generate OTP (One Time Password) and implement it using Verilog HDL. To perform any online transaction using debit or credit cards, an OTP is sent to the client via SMS for his mobile number registered at the bank, then the client enters this OTP to complete the transaction. This OTP is generated at Bank server and sent to the client mobile operator. Once the OTP is generated it should be protected during the transmission from cyber attacks such as phishing, malware Trojans, etc. before it reaches the client to maintain confidentiality and integrity of information. This algorithm uniquely specifies the steps to encrypt the plain text into cryptographic cipher and to decrypt this cipher text back into original form. The proposed modified method is for improving the security.

  • References

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  • How to Cite

    Noorbasha, F., Kishore, K. H., Naveen, T., Anusha, A. S., Manisha, Y., Revathi, K., & Manasa, M. (2018). Implementation of modified Feistel block cipher for OTP generation using Verilog HDL. International Journal of Engineering & Technology, 7(2.8), 392-396. https://doi.org/10.14419/ijet.v7i2.8.10678

    Received date: 2018-03-26

    Accepted date: 2018-03-26

    Published date: 2018-03-19