FPGA based asymmetric crypto system design

 
 
 
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    In the network security system cryptography plays a vital role for the secure transmission of information. Cryptography is a process of integrating and transferring the data to the genuine users against any attacks. There are two types of Cryptographic algorithm: Symmetric and Asymmetric algorithms. In the symmetric type cryptography, single key is used for both encryption and decryption. Symmetric algorithms are fast and simple. Asymmetric cryptographic algorithm uses different keys such as public key to encrypt the message at sender and private key which is known only to receiver for decrypting the encrypted message. Asymmetric algorithms are more secure and difficult, to decrypt the message unless hacker acquires the knowledge of private key. A new Asymmetric algorithm with Error Detection and Correction mechanism is proposed that can reduce hardware, and improves decryption time and security. Proposed Asymmetric algorithm uses the few properties of: RSA, Diffie-Hellman and ElGamal Algorithms. Performance of asymmetric algorithms is compared with proposed algorithm, which is designed using Verilog HDL. Algorithms are synthesized, simulated, implemented using Vivado and targeted for Artix-7 XC7A100T-1CSG324Carchitecture.Chipscope Pro logic analyzer-Virtual Input Output core is binded to design for hardware debugging, to monitor and capture the output signals at selected specified state by applying random input stimuli at runtime in Nexys4 DDR FPGA Board.


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Article ID: 10788
 
DOI: 10.14419/ijet.v7i1.1.10788




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