Implementation of Fast Convolution using Robust Vedic Multiplier of Radix-2

  • Authors

    • Damarla Paradhasaradhi
    • Bharinala Haridhar
    • A V. Sreekanth Reddy
    • Dudipalli Sri Charan
    • Atyam Lekhaz
    2018-03-18
    https://doi.org/10.14419/ijet.v7i2.7.10895
  • Convolution, De-Noising, Edge Detection, Full Adder, Robust Vedic Multiplier.
  • Convolution is an algorithm which is mainly used in video, audio and image processing. Convolution calculation is simple in steps however it consumes a lot of memory as well as power in the computational process. It is a mathematical algorithm which is also used in the applications like filtering, edge detection, de-noising, compression etc., as it can be exploit computational power. In this paper, we implemented the speed of discrete linear convolution using robust Vedic multiplier which is one of the fastest multipliers with two finite-length sequences. By implementing convolution with Vedic multiplier power, area and delay are reduced. This implementation process can be realized by simplifying the convolution building block.

     

     

  • References

    1. [1] Pankaj Katkar, Sridhar T N, Sharath G M, Sivanantham S* and Sivasankaran K “VLSI Implementation of Fast Convolution†2015 Online International Conference on Green Engineering and Technologies (IC-GET 2015).

      [2] Sushma R. Huddar and Sudhir Rao, Kalpana M, Surabhi Mohanâ€Novel High speed Vedic Mathematics Multiplier using Compressorsâ€, 978-1-4673-5090-7/13/2013 IEEE.

      [3] Yuke Wang, Keshab Parhi “Explicit Cook-Toom Algorithm for Linear' Convolution†0-7803-6293-4/00/ 2000 IEEE.

      [4] Deyun Wei, Student Member, IEEE, Qiwen Ran, Yuanmin Li, Jing Ma, and Liying Tan “A Convolution and Product Theorem for the Linear Canonical Transform†IEEE SIGNAL PROCESSING LETTERS, VOL. 16, NO. 10, OCTOBER 2009.

      [5] Zdenka Babic', Danilo P. Mandic2†A Fast Algorithm for Linear Convolution of Discrete Time Signals†19-21 September 2001, Ni5, Yugoslavia.

      [6] Khader Mohammad, Sos Agaian†Efficient FPGA implementation of convolution†Proceedings of the 2009 IEEE International Conference on Systems, Man, and Cybernetics San Antonio, TX, USA - October 2009.

      [7] Karishma P Dighorikar, S. L. Haridas†Area Efficient Architecture for Convolution Using Vedic Mathematics†International Journal of Science and Research (IJSR), ISSN (Online): 2319-7064.

      [8] Jyoti Prakash Mohanty, Ritisnigdha Das, Siba Kumar Panda “Design and Simulation of Convolution using Booth encoder Wallace Tree Multiplier†IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834,p- ISSN: 2278-8735. PP 42-46.

      [9] Kaustubh Manikrao Gaikwad, Mahesh Shrikanth Chavan “Analysis of Array Multiplier and Vedic Multiplier using Xilinx†Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 5 – No.1, May 2016.

      [10] M Siva Kumar, Sanath Kumar Tulasi, N Srinivasulu, Vijaya Lakshmi Bandi, K Hari Kishore “Bit wise and Delay of vedic multiplier†International Journal of Engineering & Technology,pp 26-30.

      [11] Lee Shing Jie1, a) and Siti Hawa Ruslan1, b)†A 2x2 Bit Vedic Multiplier with Different Adders in 90nm CMOS Technology†Published by AIP Publishing. 978-0-7354-1563-8.

      [12] Damarla Paradhasaradhi, M. Prashanthi and N Vivek, “A modified Wallace tree multiplier using efficient square root carry select adderâ€, IEEE International conference in green computing, communication and electrical engineering, March 2014.

      [13] Khushbu Maheshwari, Prof. Mukesh Tiwari†Design and Implementation of 4-bit Array Multiplier for Low Power in 45nm CMOS Technology†International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 3 Issue 4, April – 2014.

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  • How to Cite

    Paradhasaradhi, D., Haridhar, B., V. Sreekanth Reddy, A., Sri Charan, D., & Lekhaz, A. (2018). Implementation of Fast Convolution using Robust Vedic Multiplier of Radix-2. International Journal of Engineering & Technology, 7(2.7), 626-630. https://doi.org/10.14419/ijet.v7i2.7.10895