CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

  • Authors

    • J Lakshmi Prasanna
    • V Sahiti
    • E Raghuveera
    • M Ravi Kumar
    2018-03-18
    https://doi.org/10.14419/ijet.v7i2.7.10915
  • ANT Circuits, Fast Adders, Parallel Prefix Tree Structure, Priority Encoder and Transmission Gates

  • A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

     

  • References

    1. [1] Saleh Abdel and Gordon-Ross , ‘Scalable Digital CMOS Comparator Using a Parallel Prefix Tree’ in IEEE Transactions On VLSI Systems ,VOL.21,NO.11,NOVEMBER 2013

      [2] S.Chandrashekar and J.Lakshmi Prasanna ‘128 Bit Parallel Prefix Tree Structure Comparator’ International Journal of Research in Engineering and Science,VOL.3,Issue 10

      [3] Y.Sheng and W.Wang ‘Design and implementation of compression algorithm comparator for digital image processing on component’Int.Conf.Young Coumput.Sci,Nov 2008

      [4] B.Parhami ‘Efficient hamming weight comparators for binary vectors based on accumulative and up/down parallel counters’ IEEE transactions.Circuits Syst,Vol.56,FEB2009

      [5] A.H>Chan and G.W.Roberts ‘A Jitter characterization system using a component invariant Vernier delay line’ IEEE Trans on VLSI,Vol 12,Jan 2004

      [6] M.Abramovici,M.A.Breuer and A.D.Frriedman ‘Digital Sytems Testing and Testable Design,Piscataway,NJ:IEEE press 1990

      [7] H.Suzuki, C.H.Kim and K.Roy ‘Fast tag comparator using diode parttioned domino for 64-bit microprocessor’ IEEE Trans.Circuits Systems,Vol.54,Feb 2007.

      [8] V. Ponomarev, G. Kucuk, O. Ergin, and K. Ghose ‘Energy efficient comparators’

      [9] H. L. Helms ‘High Speed (HC/HCT) CMOS Guide .Englewood Cliffs NJ: Prentice-Hall, 1989.

      [10] TEXAS INSTRUMENTS SN7485 4-bit Magnitude Comparators.

      [11] K. W. Glass ‘Digital comparator circuit’ U.S. Patent 5 260 680, Feb.13, 1992.

      [12] D. Norris ‘Comparator circuit’ U.S. Patent 5 534 844, Apr. 3, 1995.

      [13] W.Guangjie,S.Shimin and J. Lijiu, ‘New efficient design of digital comparator’ 2nd Int. Conf. Appl. Specific Integr. Circuits, 1996,pp. 263–26

      [14] Bala Dastagiri, N. And Hari Kishore, K., 2016. Analysis Of Low Power Low Kickback Noise Dynamic Comparators In Pacemakers. Indian Journal Of Science And Technology, 9(44),.

      [15] Bala Dastagiri, N. And Hari Kishore, K., 2016. Reduction Of Kickback Noise In Latched Comparators For Cardiac Imds. Indian Journal Of Science And Technology, 9(43),.

      [16] Hussain, S.N. And Kishore, K.H., 2016. Computational Optimization Of Placement And Routing Using Genetic Algorithm. Indian Journal Of Science And Technology, 9(47),.

      [17] Mudavath, M. And Harikishore, K., 2016. Design Of Cmos Rf Front-End Of Low Noise Amplifier For Lte System Applications. Asian Journal Of Information Technology, 15(20), Pp. 4040-4047.

      [18] Murali, A., Kakarla, H.K. And Venkat Reddy, D., 2016. Integrating Fpgas With Trigger Circuitry Core System Insertions For Observability In Debugging Process. Journal Of Engineering And Applied Sciences, 11(12), Pp. 2643-2650.

      [19] Bala Gopal, P., Hari Kishore, K., Kalyana Venkatesh, R.R. And Harinath Mandalapu, P., 2015. An Fpga Implementation Of Onchip Uart Testing With Bist Techniques. International Journal Of Applied Engineering Research, 10(14), Pp. 34047-34051.

      [20] Bharadwaj, M. And Kishore, H., 2017. Enhanced Launch-Off-Capture Testing Using Bist Design. Journal Of Engineering And Applied Sciences, 12(3), Pp. 636-643.

      [21] Vundavilli, P.R., Parappagoudar, M.B., Kodali, S.P. And Benguluri, S., 2012. Fuzzy Logic-Based Expert System For Prediction Of Depth Of Cut In Abrasive Water Jet Machining Process. Knowledge-Based Systems, 27, Pp. 456-464.

      [22] Kilaru, S., Harikishore, K., Sravani, T., Anvesh Chowdary, L. And Balaji, T., 2014. Review And Analysis Of Promising Technologies With Respect To Fifth Generation Networks, 1st International Conference On Networks And Soft Computing, ICNSC 2014 - Proceedings 2014, pp. 248-251.

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  • How to Cite

    Lakshmi Prasanna, J., Sahiti, V., Raghuveera, E., & Ravi Kumar, M. (2018). CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure. International Journal of Engineering & Technology, 7(2.7), 647-651. https://doi.org/10.14419/ijet.v7i2.7.10915