CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

  • Authors

    • J Lakshmi Prasanna
    • V Sahiti
    • E Raghuveera
    • M Ravi Kumar
    2018-03-18
    https://doi.org/10.14419/ijet.v7i2.7.10915
  • ANT Circuits, Fast Adders, Parallel Prefix Tree Structure, Priority Encoder and Transmission Gates

  • Abstract

    A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

     

  • References

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  • How to Cite

    Lakshmi Prasanna, J., Sahiti, V., Raghuveera, E., & Ravi Kumar, M. (2018). CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure. International Journal of Engineering & Technology, 7(2.7), 647-651. https://doi.org/10.14419/ijet.v7i2.7.10915

    Received date: 2018-04-02

    Accepted date: 2018-04-02

    Published date: 2018-03-18