Development of Framer/Deframer for 5Gbps JESD204B Soft IP

  • Authors

    • Ingrid B. Escabal
    • Edzel G. Raffiñan
    • Jefferson A. Hora
    2018-04-03
    https://doi.org/10.14419/ijet.v7i2.11.11000
  • JESD204B, Soft IP, FPGA, Lattice Semiconductor, RTL, converter

  • Abstract

    This paper aimed to modify and redesign theJESD204B Full System of Lattice Semiconductor, particularly the TX deframer and RX framer modules used for the 3Gbps JESD204B soft IP to support the recently released 5Gbps JESD204B Soft IP. The modified full system instantiating the new 5Gbps JESD204B Soft IP had to be tested for functionality through RTL and gate simulation and tested for timing through Static Timing Analysis.

     

    The transaction layer’s RX framer, TX deframer, and the clock generator modules were identified to be the major blocks of the full system affected by the change in the soft IP. These were redesigned, followed by RTL and gate simulation of the full system. STA was checked through the Lattice Diamond tool. The system passed the simulation tests. Also, STA results showed that timing was still relaxed even if the lane speed was increased, ensuring that timing requirements are achieved by the device. It is recommended that the full system’s other blocks, and the testbench for the JESD204B and other soft IP products be investigated to operate at a higher clock frequency without violating the timing requirements and constraints of the ECP5 device.

     

     

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  • How to Cite

    B. Escabal, I., G. Raffiñan, E., & A. Hora, J. (2018). Development of Framer/Deframer for 5Gbps JESD204B Soft IP. International Journal of Engineering & Technology, 7(2.11), 21-26. https://doi.org/10.14419/ijet.v7i2.11.11000

    Received date: 2018-04-03

    Accepted date: 2018-04-03

    Published date: 2018-04-03