Design of high speed low power optimized square root BK adder

  • Abstract
  • Keywords
  • References
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  • Abstract

    Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these two regarding area and power is Carry Select Adder (CSA). Parallel prefix adders are used to obtain quick results. In this course work, a new methodology to Modified Square Root Brent Kung adder (MSR-BK-A) is proposed to design an optimized adder and to calculate various performance parameters like area, power and delay for square root adder designs. By optimizing the structure of Binary-to-Excess-1 converter(BEC) and using it in Square Root BK adder, the power and delay can be reduced with a trade of in area. The simulated results conclude that, the MSR-BK-A with Modified BEC gives better performance in terms of power and delay. These designs have been simulated, verified and synthesized using Xilinx ISE 14.7 tool.


  • Keywords

    Regular Linear Brent Kung Adder (RL-BK-A); Modified Linear Brent Kung Adder (M-RL-BK-A); Regular Square Root Brent Kung Adder (RSR-BK-A); Modified Square Root Brent Kung Adder (MSR-BK-A); New Optimized Square Root Brent Kung Adder (N-OSR-BK-A).

  • References

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Article ID: 11289
DOI: 10.14419/ijet.v7i2.12.11289

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