Design of high speed low power optimized square root BK adder

  • Authors

    • Ranjith B Gowda
    • R M Banakar
    2018-04-03
    https://doi.org/10.14419/ijet.v7i2.12.11289
  • Regular Linear Brent Kung Adder (RL-BK-A), Modified Linear Brent Kung Adder (M-RL-BK-A), Regular Square Root Brent Kung Adder (RSR-BK-A), Modified Square Root Brent Kung Adder (MSR-BK-A), New Optimized Square Root Brent Kung Adder (N-OSR-BK-A).
  • Abstract

    Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these two regarding area and power is Carry Select Adder (CSA). Parallel prefix adders are used to obtain quick results. In this course work, a new methodology to Modified Square Root Brent Kung adder (MSR-BK-A) is proposed to design an optimized adder and to calculate various performance parameters like area, power and delay for square root adder designs. By optimizing the structure of Binary-to-Excess-1 converter(BEC) and using it in Square Root BK adder, the power and delay can be reduced with a trade of in area. The simulated results conclude that, the MSR-BK-A with Modified BEC gives better performance in terms of power and delay. These designs have been simulated, verified and synthesized using Xilinx ISE 14.7 tool.

     

  • References

    1. [1] G. Sivannarayana, R. babu Maddasani, and P. Ch, “Design and implementation of carry tree adders using low power fpgas,†International Journal of Advanced Research in Computer Engineering & Technology (IJARCET), vol. 1, no. 7, pp. Pp–295, 2012.

      [2] S. Parmar and K. P. Singh, “Design of high speed hybrid carry select adder,†in Advance Computing Conference (IACC), 2013 IEEE 3rd International, pp. 1656–1663, IEEE, 2013.

      [3] Y. He, C.-H. Chang, and J. Gu, “An area efficient 64-bit square root carry-select adder for low power applications,†in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, pp. 4082–4085, IEEE, 2005.

      [4] M. Snir, “Depth-size trade-offs for parallel prefix computation,†Journal of Algorithms, vol. 7, no. 2, pp. 185–201, 1986.

      [5] D. J. Jackson and S. J. Hannah, “Modelling and comparison of adder designs with verilog hdl,†in System Theory, 1993. Proceedings SSST’93. Twenty-Fifth Southeastern Symposium on, pp. 406–410, IEEE, 1993.

      [6] B. W. Y. Wei and C. D. Thompson, “Area-time optimal adder design,†IEEE transactions on Computers, vol. 39, no. 5, pp. 666–675, 1990.

      [7] H. Zhu, C.-K. Cheng, and R. Graham, “Constructing zero-deficiency parallel prefix adder of minimum depth,†in Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific, vol. 2, pp. 883–888, IEEE, 2005.

      [8] V. Dave, E. Oruklu, and J. Saniie, “Performance evaluation of flagged prefix adders for constant addition,†in Electro/information Technology, 2006 IEEE International Conference on, pp. 415–420, IEEE, 2006.

      [9] R. P. Brent and H.-T. Kung, “A regular layout for parallel adders,†IEEE transactions on Computers, no. 3, pp. 260–264, 1982.

      [10] A. Siliveru and M. Bharathi, “Design of kogge-stone and brent-kung adders using degenerate pass transistor logic,†International Journal of Emerging Science and Engineering, vol. 1, no. 4, pp. 38–41, 2013.

      [11] Pallavi saxena, “Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder,†2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA).

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  • How to Cite

    B Gowda, R., & M Banakar, R. (2018). Design of high speed low power optimized square root BK adder. International Journal of Engineering & Technology, 7(2.12), 240-243. https://doi.org/10.14419/ijet.v7i2.12.11289

    Received date: 2018-04-08

    Accepted date: 2018-04-08

    Published date: 2018-04-03