Implementation of ISLIP scheduler for NOC router on FPGA

  • Authors

    • Priti M. Shahane
    • Narayan Pisharoty
    2018-04-03
    https://doi.org/10.14419/ijet.v7i2.12.11302
  • System on Chip (SOC), Network on Chip (NOC), Router, Scheduler, Islip Scheduler, Round Robin Scheduler

  • Abstract

    Network on chip (NoC) effectively replaces a traditional bus based architecture in System on chip (SoC). The NoC provides a solution to the communication bottleneck of the bus based interconnection in SoC, where large numbers of Intellectual modules are integrated on a single chip for better performance. In NoC architecture, the router is a dominant component, which should provide contention free architecture with low latency. The router consists of input block, scheduler and crossbar switch. The design of scheduler leads the performance of the NoC router in terms of latency. Hence the starvation free scheduler is paramount importantin the NoC router design. iSLIP (Iterative serial line internet protocol) scheduler has programmable priority encoder which makes it fast and efficient scheduler over round robin arbiter. In this paper 2x4 NoC router using iSLIPscheduler is proposed. The proposed design is implemented using the Verilog programming on Xilinx Spartan 3 device.

     

  • References

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  • How to Cite

    M. Shahane, P., & Pisharoty, N. (2018). Implementation of ISLIP scheduler for NOC router on FPGA. International Journal of Engineering & Technology, 7(2.12), 268-270. https://doi.org/10.14419/ijet.v7i2.12.11302

    Received date: 2018-04-09

    Accepted date: 2018-04-09

    Published date: 2018-04-03