An efficient architecture of iterative logarithm multiplier
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2018-04-12 https://doi.org/10.14419/ijet.v7i2.16.11410
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Improved operand decomposition, Iterative logarithm multiplier, Leading one detector, Mitchell method, Seamless pipeline. -
Abstract
Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell’s algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell’s algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % less ADP, 25.08 %, 38.08 % and 46.72 % less energy for 8, 16, and 32 bits architecture respectively in comparison of the reported ILM. The importance of LODs and seamless pipeline has been shown in an efficient architecture of Mitchell's based ILM.
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References
[1]. Pappalardo F, Visalli G & Scarana M (2004), An application-oriented analysis of power/precision tradeoff in fixed and floating-point arithmetic units for VLSI processors, in Proc. IASTED Conf. Circuits, Signals, and Systems, pp. 416 -421.
[2]. Kouretas I, Basetas C & Paliouras V (2013), Low-power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters, IEEE Transactions on Computers, 62, 2196–2209.
[3]. Saha P, Banerjee A, Dandapat A & Bhattacharyya P (2014), High speed multiplier using high accuracy floating point logarithmic number system, Scientia Iranica Transactions D: Computer Science & Engineering and Electrical Engineering, 21, 3, 826–841.
[4]. Suzuki H, Morinaka H, Makino H, Nakase Y, Mashiko K & Sumi T (1996), Leading-Zero Anticipatory Logic for High Speed Floating Point Addition, IEEE J. Solid-State Circuits, 31, 8, 1157-1164.
[5]. Abed KH & Sifred R.E (2006), VLSI Implementations of Low-Power Leading-One Detector Circuits, Proceedings of the IEEE Southeast Conference, 279-284.
[6]. Kunaraj K & Seshasayanan R (2013), Leading one detectors and leading one position detectors-An evolutionary design methodology, Canadian journal of electrical and computer engineering, 36, 3, 103-110.
[7]. Brubaker T A & Becker J C (1975), Multiplication Using Logarithms Implemented with Read-Only-Memory, IEEE Trans. Computers, 761-766.
[8]. Arnold M, Bailey T & Cowles J (2003), Error Analysis of the Kmetz / Maenner Algorithm, J. VLSI Signal Processing, 37-53.
[9]. Mitchell J N, Computer Multiplication and Division using Binary Logarithms, IRE Trans. Electronic Computers, 11, 6, 512-517.
[10]. Paul S, Jayakumar N & Khatri SP (2009), A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations., IEEE Transactions on Very Large Scale Integration Systems, 17, 2, pp. 269–277.
[11]. Kostopoulos DK (1991), An Algorithm for the Computation of Binary Logarithms, IEEE Transaction on Computers, 40, 11, 1267-1270.
[12] Kouretas I, Basetas C & Paliouras V (2013), Low-power Logarithmic Number System Addition/Subtraction and their Impact on Digital Filters, IEEE Transactions on Computers, 62, 11, 2196–2209.
[13]. Taylor FJ, Gill R & Joseph J (1988), A 20 Bit Logarithmic Number System Processor, IEEE Trans. Computers, 37, 2, 190-200.
[14] Tang PTP (1991), Table-Lookup Algorithms for Elementary Functions and Their Error Analysis, IEEE 10th Symposium on Computer Arithmetic, Grenoble, New York, 232-236.
[15]. Schulte MJ & Swartzlander EE (1994), Hardware Designs for Exactly Rounded Elementary Functions, IEEE Transactions on Computers, 43, 8, 964-973.
[16]. Stine JE & Schulte MJ (1999), The Symmetric Table Addition Method for Accurate Function Approximation, Journal of VLSI Signal Processing Systems, 21, 2, 167–177.
[17]. Pineiro JA, Ercegovac MD & Bruguera JD (2004), Algorithm and Architecture for Logarithm, Exponential, and Powering Computation, IEEE Transaction on Computers, 53, 9, 1085–1096.
[18]. Fu H, Mencer O & Luk W, FPGA Designs with Optimized Logarithmic Arithmetic, IEEE Transactions on Computers, 59, 7, 1000-1006.
[19]. Ismail RC & Coleman JN (2011), ROM-Less LNS, In Proceedings of IEEE Symposium on Computer Arithmetic,Tubingen, New York, 43-51.
[20]. Arnold MG & Collange S (2011), A Real/Complex Logarithmic Number System ALU, IEEE Transactions on Computers, 60, 2, 202-213.
[21]. Durgesh Nandan, Kanungo J. & Mahajan A (2017), An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition, Integration, the VLSI Journal, 58,134-141.
[22]. Bulic P, Babic Z & Avramovic A, A simple pipelined logarithmic multiplier, IEEE International Conference on Computer Design (ICCD), 235-240.
[23]. Babic Z, Avramovic A & Bulic P (2011), An iterative logarithmic multiplier, Microprocessors and Microsystems, 35, 1, 23-33.
[24]. Agrawal RK. & Kittur HM (2013), ASIC based logarithmic multiplier using iterative pipelined architecture, IEEE Conference on Information & Communication Technologies, 362-366.
[25]. Durgesh Nandan, Kanungo J & Mahajan A (2017), An efficient VLSI architecture for Iterative Logarithmic Multiplier, IEEE 4th International conference on signal processing and integrated networks (SPIN), 419-423.
[26]. Johansson K, Gustafsson O & Wanhammar L (2008), Implementation of Elementary Functions for Logarithmic Number Systems, IET Computer & Digital Techniques, 2, 4, 295-304.
[27]. SanGregory SL, Siferd RE, Brother C & Gallagher D (1999), Low-Power Logarithm Approximation with CMOS VLSI Implementation, Proc. IEEE Midwest Symp. Circuits and Systems, 381-391.
[28]. Hall EL, Lynch DD & Dwyer III SJ (1970), Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications, IEEE Trans. Computers, 19, 2, 97-105.
[29]. Swartzlander E & Alexopoulos A (1975), The sign/logarithm number system, IEEE Trans. Comput., C, 1238–1242, 1975.
[30]. Yu LK & Lewis DM (1991), A 30-b Integrated Logarithmic Number System Processor, IEEE Journal of Solid State Circuits, 26, 10, 1433-1440.
[31]. Abed KH & Sifred RE (2003), CMOS VLSI Implementation of a Low-Power Logarithmic Converter, IEEE Transactions on Computers, 52, 11, 1421-1433.
[32]. Mahalingam V & Rangantathan N, Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition, IEEE Transactions on Computers, 55, 2, 1523-1535.
[33]. Durgesh Nandan, Kanungo J & Mahajan A (2016), An Efficient VLSI architecture design for antilogarithmic converter by using the error correction scheme, IET International conference on signal processing (ICSP), DOI: 10.1049/cp.2016.1445.
[34]. Durgesh Nandan, Mahajan A & Kanungo J (2017), An efficient antilogarithmic converter by using 11-regions error correction schemeâ€, IEEE 4th International signal processing, Computing and Control (ISPCC), 118-121.
[35]. Akhter P., Bandewar S & Durgesh Nandan (2016), Logarithmic Multiplier: An Analytical Review, International Journal of Engineering Research, 5, 721-723.
[36]. Durgesh Nandan, Kanungo J & Mahajan A (2018), 65 years journey of logarithm multiplier, International Journal of Pure and Applied Mathematics, vol. 118, 261-266.
[37]. Durgesh Nandan, Kanungo J & Mahajan A (2018), An efficient architecture of leading one detector, International Journal of Pure and Applied Mathematics, vol. 118, pp: 267-272, 2018.
[38]. Durgesh Nandan, Kanungo J & Mahajan A (2017), Implementation of Leading One Detector based on reversible logic for logarithmic arithmetic, International Journal of Computer Applications, 173, 8, 40-45.
[39]. Mehar PK, Seamless Pipelining of DSP Circuits, Circuits System and Signal Processing, 35, 1147-1162.
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How to Cite
Nandan, D., Kanungo, J., & Mahajan, A. (2018). An efficient architecture of iterative logarithm multiplier. International Journal of Engineering & Technology, 7(2.16), 24-28. https://doi.org/10.14419/ijet.v7i2.16.11410Received date: 2018-04-12
Accepted date: 2018-04-12
Published date: 2018-04-12