Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

  • Authors

    • Anshu Gupta
    • Lalita Gupta
    • R K. Baghel
    2018-04-12
    https://doi.org/10.14419/ijet.v7i2.16.11413
  • Continuous time sigma delta modulator SDM/DSM, analog to digital converter, CMOS process, three stage OTA, Sub threshold, integrator, dynamic standard comparator, two tail transistors, Low power circuit, digital-to-analog converter, oversampling converte

  • Abstract

    A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator.  We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/   and with low power consumption of 296.72nW.  A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

  • References

    1. [1] H. Tao, L. Toth, and J. M. Khoury, "Analysis of timing jitter in bandpass sigma-delta modulators," IEEE Trans. Circuits Syst. II, vol. 46, no. 8, pp. 991-1001, 1999.
      [2] M. Ortmanns, F. Gerfers, and Y. Manoli, "A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback," in IEEE European Solid-State Circuits Conf. ESSCIRC, 2003, pp. 249- 252.
      [3] R. Schreier and B. Zhang, "Delta-sigma modulators employing continuous-time circuitry," IEEE Trans. Circuits Syst. I, vol. 43, no. 4, pp. 324-332, 1996.
      [4] F. Gerfers, M. Ortmanns, and Y. Manoli, "A 1.5-V 12-bit powerefficient continuous-time third-order ?? modulator," IEEE J. SolidState Circuits, vol. 38, no. 8, pp. 1343-1352, 2003
      [5] R. T. Baird and T. S. Fiez, "Linearity enhancement of multibit ?? A/D and D/A converters using data weighted averaging," IEEE Trans. Circuits Syst. II, vol. 42, no. 12, pp. 753-762, 1995.
      [6] K. L. Chan, N. Rakuljic, and I. Galton, "Segmented dynamic element matching for high-resolution digital-to-analog conversion," IEEE Trans. Circuits Syst. I, vol. 55, no. 11, pp. 3383-3392, 2008.
      [7] N. Sun and P. Cao, "Low-complexity high-order vector-based mismatch shaping in multibit ?? ADCs," IEEE Trans. Circuits Syst. II, vol. 58, no. 12, pp. 872-876, 2011
      [8] B. Li and H. Tenhunen, "A second order sigma delta modulator using semi-uniform quantizer with 81dB dynamic range at 32x OSR," in IEEE European Solid-State Circuits Conf. ESSCIRC, 2002, pp. 579-582.
      [9] Y. Cheng, C. Petrie, B. Nordick, and D. Comer, "Multibit delta-sigma modulator with two-step quantization and segmented DAC," IEEE Trans. Circuits Syst. II, vol. 53, no. 9, pp. 848-852, 2006.
      [10] C. C. Lee, E. Alpman, S. Weaver, C.-Y. Lu, and J. Rizk, "A 66dB SNDR 15MHz BW SAR assisted ?? ADC in 22nm tri-gate CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, 2013, pp. C64-C65.
      [11] E. M. Cherry, "A new result in negative-feedback theory nd its application to audio power amplifiers," Int. J. Circuits Theor. Appl., vol. 6, pp. 265-288, 1978.
      [12] E. M. Cherry, "Nested differentiating feedback loops in simple audio power amplifier," J. Audio Eng. Soc., vol. 30, pp. 295-305, May 1982.
      [13] J. H. Huijsing and D. Linebarger, "Low-voltage operational amplifier with rail-to-rail input and output ranges," IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1144-1150, 1985.
      [14] F. Op'tEynde, P. Ampe, L. Verdeyen, and W. Sansen, "A CMOS largeswing low-distortion three-stage class AB power amplifier," IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 265-273, Feb. 1990.
      [15] R. G. H. Eschauzier and J. H. Huijsing, "A 100-MHz 100-dB operational amplifier with multipath nested miller compensation," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1709-1716, Dec. 1992.
      [16] H. Khorrambadi, J. Anidijar, and T. Peterson, "A highly efficient CMOS line driver with 80-dB linearity for ISDN U-interface applications," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1723-1729, Dec. 1992.
      [17] G. Palumbo and S. Pennisi, Feedback Amplifiers: Theory and Design. New York: Kluwer Academic, 2002.
      [18] P. Surkanti and P. Furth, "Converting a three-stage pseudoclass-AB amplifier to a true-class-AB amplifier," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 4, pp. 329-333, Apr. 2012.
      [19] S. S. Chong and P. K. Chan, "Cross feedforwardcascode compensation for low-power three-stage amplifier with large capacitive load," IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2227-2234, Sep. 2012.
      [20] Z. Yan, P.-I. Mak, M.-K. Lau, and R. P. Martins, "A 0.016-mm 144-ï¾µW three-stage amplifier capable of driving 1-to-15 nF capacitive load with 0.95-MHz GBW," IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 527-540, Feb. 2013.
      [21] M. Tan and W.-H. Ki, "A cascode miller-compensated three-stage amplifier with local impedance attenuation for optimized complex-pole control," IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 440-449, 2015.
      [22] F. You, S. Embabi, and E. Sanchez-Sinencio, "Multistage amplifier topologies with nested Gm-C compensation," IEEE J. Solid-State Circuits, vol. 32, pp. 2000-2011, Dec. 1997.
      [23] H.-T. Ng, R. Ziazadeh, and D. Allstot, "A multistage amplifier technique with embedded frequency compensation," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 339-347, Mar. 1999.
      [24] K. N. Leung and P. K. T. Mok, "Nested Miller compensation in lowpower CMOS design," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, pp. 388-394, Apr. 2001.
      [25] K. N. Leung and P. K. T. Mok, "Analysis of multistage amplifier-frequency compensation," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 9, pp. 1041-1056, Sep. 2001.
      [26] G. Palumbo and S. Pennisi, "Design methodology and advances in Nested-Miller compensation," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 7, pp. 893-903, Jul. 2002.
      [27] A. D. Grasso, G. Palumbo, and S. Pennisi, "Three-stage CMOS OTA for large capacitive loads with efficient frequency compensation scheme," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 10, pp. 1044-1048, Oct. 2006.
      [28] A. D. Grasso, G. Palumbo, and S. Pennisi, "Analytical comparison of frequency compensation techniques in three-stage amplifiers," Int. J. Circuit Theor. Appl., vol. 36, no. 1, pp. 53-80, Jan. 2008.
      [29] S. Guo and H. Lee, "Dual active-capacitive-feedback compensation for low-power large-capacitive-load three-stage amplifiers," IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 452-464, Feb. 2011.
      [30] R. Mita, G. Palumbo, and S. Pennisi, "Design guidelines for reversed Nested Miller compensation in three-stage amplifiers," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, pp. 227-233, May 2003.
      [31] K.-P. Ho, C.-F. Chan, C.-S. Choy, and K.-P. Pun, "Reversed Nested Miller compensation with voltage buffer and nulling resistor," IEEE J. Solid-State Circuits, vol. 38, pp. 1735-1738, Oct. 2003.
      [32] A. D. Grasso, D. Marano, G. Palumbo, and S. Pennisi, "Improved reversed Nested Miller compensation technique with voltage buffer and nulling resistor," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 5, pp. 382-386, May 2007.
      [33] D. Marano, G. Palumbo, and S. Pennisi, "An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive- load three-stage OTAs," in Proc. ICECS '09, Hammamet, Tunisia, Dec. 2009, pp. 121-131.
      [34] A. D. Grasso, G. Palumbo, and S. Pennisi, "Advances in reversed Nested Miller compensation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 7, pp. 1459-1470, Jul. 2007.
      [35] M. Shen, P. Lan, and P. Huang, "A 1-V CMOS pseudo-differential amplifier with multiple common-mode stabilization and frequency compensation loops," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 5, pp. 409-413, May 2008.
      [36] A. Garimella, M. W. Rashid, and P. Furth, "Reversed Nested Miller compensation using current buffers in three-stage LDO," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 4, pp. 250-254, Apr. 2010.
      [37] A. D. Grasso, D. Marano, G. Palumbo, and S. Pennisi, "Analytical comparison of reversed nested Miller frequency compensation techniques," Int. J. Circuit Theor. Appl., vol. 38, no. 7, pp. 709-737, 2010.
      [38] S. O. Cannizzaro, A. D. Grasso, R. Mita, G. Palumbo, and S. Pennisi, "Design procedures for three-stage CMOS OTAs with Nested-Miller compensation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 5, pp. 933-940, May 2007.
      [39] Ay, S.U. (2011). A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS. Int. J. Analog Integr. Circuits Signal Process, 66(2), 213-221.
      [40] Goll, B.; and Zimmermann, H. (2009).A comparator with reduced delay time in65-nm CMOS for supply voltages down to 0.65. IEEE Trans. Circuits Syst. II, Exp. Briefs, 56(11), 810-814.
      [41] Maymandi-Nejad, M.; and Sachdev, M. (2003). 1-bit quantiser with rail to rail input range for sub-1V modulators. IEEE Electron. Lett., 39(12), 894-895.
      [42] Mesgarani, A.; Alam, M. N.; Nelson, F. Z.; and Ay, S. U. (2010). Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS. Proc. IEEE Int. Midwest Symp. Circuits Syst. Dig. Tech. Papers, 893-896.
      [43] Blalock, B. J. (2000). Body-driving as a Low-Voltage Analog Design Technique for CMOS technology. Proc. IEEE Southwest Symp. Mixed-Signal Design, 113-118.
      [44] Goll, B.; and Zimmermann, H. (2009). A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47?W at 0.6V. Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 328-329.
      [45] Goll, B.; and Zimmermann, H. (2007). Low-power 600MHz comparator for 0.5 V supply voltage in 0.12 ?m CMOS. IEEE Electron. Lett., 43(7), 388-390.
      [46] Shinkel, D.; Mensink, E.; Klumperink, E.; Tuijl , E. Van; and Nauta, B. (2007). A double-tail latch-type voltage sense amplifier with 18ps Setup +Hold time. Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 314-315.
      [47] Okaniwa, Y.; Tamura, H.; Kibune, M.; Yamazaki, D.; Cheung, T.S.; Ogawa, J.; Tzartzanis, N.; Walker, W. W.; and Kuroda, T. (2005). A 40Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE J. Solid-State Circuits, 40(8), 1680-1687.
      [48] Goll, B.; and Zimmermann, H. (2007). A 0.12 ?m CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6 GHz. Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 316-317.
      [49] Nuzzo, P.; Bernardinis, F.D.; Terreni, P.; and Van der Plas, G. (2008). Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Trans. Circuits Syst. I, Reg. Papers, 55 (6), 1441-1454.
      [50] Nikoozadeh, A.; and Murmann, B. (2006). An analysis of latched comparator offset due to load capacitor mismatch. IEEE Trans. Circuits Syst. II, Exp. Briefs, 53(12), 1398 1402.
      [51] Babayan-Mashhadi, S.; and Lotfi, R. (2012). An offset cancellation technique for comparators using body-voltage trimming. Int. J. Analog Integr. Circuits Signal Process., 73(3), 673-682.
      [52] He, J.; Zhan, S.; Chen, D.; and Geiger, R. J. (2009). Analyses of static and dynamic random offset voltages in dynamic comparators. IEEE Trans. Circuits Syst. I, Reg. Papers, 56(5), 911-919.
      [53] Kim, J.; Leibowits, B. S.; Ren, J.; and Madden, C. J. (2009). Simulation and analysis of random decision errors in clocked comparators. IEEE Trans. Circuits Syst. I, Reg. Papers, 56(8), 1844-1857.
      [54] Figueiredo, P. M.; and Vital, J. C. (2006). Kickback noise reduction technique for CMOS latched comapartors. IEEE Trans. Circuits Syst. II, Exp. Briefs, 53(7), 541-545.
      [55] Wicht, B.; Nirschl, T.; and Schmitt-Landsiedel, D. (2004). Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J. Solid-State Circuits, 39(7), 1148-1158.
      [56] Johns, D.; and Martin, K. (1997). Analog Integrated Circuit Design. New York, USA: Wiley.

  • Downloads

  • How to Cite

    Gupta, A., Gupta, L., & K. Baghel, R. (2018). Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator. International Journal of Engineering & Technology, 7(2.16), 38-51. https://doi.org/10.14419/ijet.v7i2.16.11413

    Received date: 2018-04-12

    Accepted date: 2018-04-12

    Published date: 2018-04-12