Design of Power Efficient 32-Bit Processing Unit

  • Authors

    • Dharmavaram Asha Devi
    • Chintala Sandeep
    • Sai Sugun L
    2018-04-12
    https://doi.org/10.14419/ijet.v7i2.16.11415
  • FPGA (Field Programmable Gate Array), HDL (Hardware Description Language), LVCMOS (Low Voltage CMOS), VIO (Virtual Input Output),
  • Abstract

    The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.

     

     

  • References

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      [5] Dharmavaram Asha Devi and Sai Sugun L, “Design, Implementation and Verification of 32-Bit ALU with VIO†IEEE International Conference on Inventive Systems and Control (ICISC), Coimbatore 2018.

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  • How to Cite

    Asha Devi, D., Sandeep, C., & Sugun L, S. (2018). Design of Power Efficient 32-Bit Processing Unit. International Journal of Engineering & Technology, 7(2.16), 52-56. https://doi.org/10.14419/ijet.v7i2.16.11415

    Received date: 2018-04-12

    Accepted date: 2018-04-12

    Published date: 2018-04-12