Design of Power Efficient 32-Bit Processing Unit

  • Authors

    • Dharmavaram Asha Devi
    • Chintala Sandeep
    • Sai Sugun L
    2018-04-12
    https://doi.org/10.14419/ijet.v7i2.16.11415
  • FPGA (Field Programmable Gate Array), HDL (Hardware Description Language), LVCMOS (Low Voltage CMOS), VIO (Virtual Input Output),

  • The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.

     

     

  • References

    1. [1] Xilinx, Virtual Input/Output v3.0 LogiCORE IP Product Guide (PG159), Vivado Design Suite, PG159 October 4, 2017 from www.xilinx.com .

      [2] Vivado Design Suite User Guide: Getting Started ,UG910 (v2017.1) April 5, 2017.

      [3] B. Pandey, J. Yadav, M. Pattanaik and N. Rajoria, "Clock gating based energy efficient ALU design and implementation on FPGA," 2013 International Conference on Energy Efficient Technologies for Sustainability, Nagercoil, pp. 93-97, 2013. doi: 10.1109/ICEETS.2013.6533362

      [4] N. Gaur, A. Mehra, D. Kamboj and D. Tyagi, “A novel implementation of 32 bit extended ALU Architecture at 28nm FPGAâ€International Conference on Emerging Trends in Communication Technologies (ETCT), Dehradun, pp. 1-4, 2016. doi: 10.1109/ETCT.2016.7882932

      [5] Dharmavaram Asha Devi and Sai Sugun L, “Design, Implementation and Verification of 32-Bit ALU with VIO†IEEE International Conference on Inventive Systems and Control (ICISC), Coimbatore 2018.

      [6] B. Pandey, J. Yadav and M. Pattanaik, "IO standard based energy efficient ALU design and implementation on 28nm FPGA," 2013 Annual IEEE India Conference (INDICON), Mumbai, pp. 1-5, 2013. doi: 10.1109/INDCON.2013.6725996.

      [7] Samir Palnitkar, Verilog HDL A Guide to Digital Design and Synthesis, Second Edition, IEEE 1364-2001 Compliant, Pearson Publications.

      [8] http://anysilicon.com/vlsi-design-flow-overview/

      [9] Dharmavaram Asha Devi, FPGA Design Flow for 8-bit ALU using Xilinx ISE, International Journal of Modren Electronics and Communication Engineering, ISSN:2321-2152, Volume.No.4, Issue.No.2, March 2016.

      [10] Pong P Chu “FPGA Prototyping By Verilog Exampes†A John Wiley & Sons, Inc., Publication.

  • Downloads

  • How to Cite

    Asha Devi, D., Sandeep, C., & Sugun L, S. (2018). Design of Power Efficient 32-Bit Processing Unit. International Journal of Engineering & Technology, 7(2.16), 52-56. https://doi.org/10.14419/ijet.v7i2.16.11415