Frequency Domain based Digital Down Conversion Architecture for Software Defined Radio and Cognitive Radio

  • Authors

    • Latha Sahukar
    • Dr M. Madhavi Latha
    2018-04-12
    https://doi.org/10.14419/ijet.v7i2.16.11422
  • Frequency Domain Filtering, Digital down conversion (DDC), Sample rate conversion

  • Abstract

    This paper presents a sampling rate digital down converter that is totally based on frequency domain processing. The proposed DDC is targeted for Software Defined Radio and Cognitive Radio architectures. The proposed architecture is based on replacement of the complex multiplication with direct rotation of the spectrum. Different aspects of frequency domain filtering are also discussed. The Xilinx Virtex-6 family FPGA, XC6VLX240T is used for the implementation and synthesis of the proposed FFT-IFFT based architecture. The overlapping in time domain at the output of the IFFT block is avoided using overlap and add method. In terms area, highly optimized implementation is observed in the proposed architecture when compared to the conventional DDC. The synthesis results have shown that the developed core works at a maximum clock rate of 250 MHz and at the same time  occupies  only 10% of the slices of  FPGA.

     

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  • How to Cite

    Sahukar, L., & M. Madhavi Latha, D. (2018). Frequency Domain based Digital Down Conversion Architecture for Software Defined Radio and Cognitive Radio. International Journal of Engineering & Technology, 7(2.16), 88-93. https://doi.org/10.14419/ijet.v7i2.16.11422

    Received date: 2018-04-12

    Accepted date: 2018-04-12

    Published date: 2018-04-12