Design of delay efficient Booth multiplier using pipelining

  • Authors

    • Abhishek Choubey
    • SPV Subbarao
    • Shruti B. Choubey
    2018-04-12
    https://doi.org/10.14419/ijet.v7i2.16.11423
  • Booth multiplier, Pipelining, Very-large-scale integration (VLSI).
  • Abstract

    Multiplication is one of the most an essential arithmetic operation used in numerous applications in digital signal processing and communications. These applications need transformations, convolutions and dot products that involve an enormous amount of multiplications of an operand with a constant. Typical examples include wavelet, digital filters, such as FIR or IIR. However, multiplier structures have relatively large area-delay product, long latency and significantly high power consumption compared to other the arithmetic structure. Therefore, low power multiplier design has been always a significant part of DSP structure for VLSI design. The Booth multiplier is promising as the most efficient amongst the others multiplier as it reduces the complexity of considerably than others. In this paper, we have proposed Booth-multiplier using seamless pipelining. Theoretical comparison results show that the proposed Booth multiplier requires less critical path delay compared to traditional Booth multiplier. ASIC simulation results show proposed radix-16 Booth multiplier 13% less critical path delay for word width n=16 and 17% less critical path delay compared for bit width n=32 to best existing radix-16 Booth multiplier.

     


  • References

    1. [1] Potkonjak, M., Srivastava, M., & Chandrakasan, A. (1996).Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), 151–165.

      [2] Gustafsson, O., & Wanhammar, L. (2007). Low-complexity constant multiplication using carry-save arithmetic for high-speed digital filters. In Proceeding of the 5th IEEE International Symposium on Image and Signal Processing and Analysis, (pp. 212–217) (September).

      [3] A.D.Booth (1951), A signed binary multiplication technique,Quarterly Journal of Mechanics and Applied mathematics,vol-IV,1951.

      [4] B K Mohanty, and A Choubey “Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT†Circuits System Signal Processing (CSSP) Vol.36 pp.1129–1149.(2017).

      [5] Choubey, A and Mohanty, B.K. (2017), “A Block Based Area- Delay Efficient Architecture for Multi-level Lifting 2-D DWT,†International Journal of Computer Applications†vol. 169, No.4.

      [6] Choubey, A. and Mohanty, B.K. (2017), “Novel Data Access Scheme & Efficient Parallel Architecture for Multi-level 2-D DWT,†Circuits, Systems, and Signal Processing, Springer. https://doi.org/10.1007/s00034-018-0775-y.

      [7] Elisardo Antelo, Paolo Montuschi and Alberto Nannarelli “Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction†IEEE transactions on circuits and systems- I: regular papers Volume 64 issue 2 Page(s):409 – 418.

      [8] S.R.Kuang, J.P.Wang, C.Y.Guo, Modified Booth multipliers with a regular partial product array. IEEE Trans. Circuits Syst. II Express Briefs 56(5), 404–408 (2009).

      [9] P.K.Mehar “ Seamless pipelining of DSP circuits,†Circuits system and signal processing, April 2016,Volume 35,Issue 4,pp 1147-1162.

      [10] R. Muralidharan and C. H. Chang. (2011). Radix-8 Booth encoded modulo 2n-1 multipliers with adaptive delay for high dynamic range residue number system. IEEE Transactions on Circuits and Systems I-Regular Papers, 58(5), 982-993.

  • Downloads

  • How to Cite

    Choubey, A., Subbarao, S., & B. Choubey, S. (2018). Design of delay efficient Booth multiplier using pipelining. International Journal of Engineering & Technology, 7(2.16), 94-96. https://doi.org/10.14419/ijet.v7i2.16.11423

    Received date: 2018-04-12

    Accepted date: 2018-04-12

    Published date: 2018-04-12