An Efficient MAC Architecture using Multiplier for DSP and DIP Operations
-
2018-04-12 https://doi.org/10.14419/ijet.v7i2.16.11505
-
MAC, DSP, Adders, LP VLSI, Data path. -
Abstract
DSP operations are very important part of engineering as well as medical discipline. For the designing of DSP operations Multiplication is play important role to perform signal processing operations. Multiplier is one of the critical components in the area of digital signal processing and hearing aids. So the objective is to design an efficient MAC hardware architecture using multiplier with assistance of compressors by conserving less area, power and delay. In this paper, efficient hardware architecture of MAC using a modified Wallace tree multiplier is proposed. The proposed MAC uses multiplier with novel compressor designs and adders as primitive building blocks for efficient application. Further, the Verilog-HDL coding of 8 bit MAC architecture and their FPGA implementation by Xilinx ISE 14.4 Synthesis Tool on Virtex7 kit have been done. The proposed compressor and adder based architecture used to be applied to MAC unit and in comparison to the previous design MAC unit and verified that the proposed architecture have reduce in terms of area, delay and power. The high performance is obtained by using a new hierarchical structure, these adders are called compressors. These compressors make the multipliers faster as compared to the conventional design used in Engineering, Science & Technology as well as medical discipline.
-
References
[1] Omondi A R.†Computer Arithmetic Systemsâ€. Englewood Cliffs, NJ: Prentice-Hall, 1994.
[2] Ping-hua C, Juan Z. "High-speed Parallel 32×32-bMultiplier Using a Radix-16 Booth Encoder," Intelligent Information Technology Application Workshops, 2009.IITAW '09. Third International Symposium on, 2009, pp.406, 409.
[3] Kiwon Choi; Minkyu Song, "Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder," Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, vol.2, no., pp.701, 704 vol. 2, 6-9 May 2001.
[4] S. D. Pezaris, "A 40-ns 17-bit by 17-bit array multipliers," IEEE Transactions on Computers, vol. 20, pp. 442-447, April 1971].
[5] P. Aliparast, Z. D. Koozehkanani, and F. Nazari, “An ultra-high speed digital 4-2 compressor in 65-nm CMOS,†International Journal of Computer Theory and Engineering, vol. 5, no. 4, pp. 593–597, 2013.
[6] N. W. Harris David, CMOS VLSI Design—A Circuits & System Perspective, Pearson Education, 2008.
[7] Tung Thanh Hoang; Sjalander, M.; Larsson-Edefors, P., "A High-Speed, Energy-Efficient Two-Cycle Multiply Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.57, no.12,pp.3073,3081, Dec. 2010.
[8] Rajput, R.P. Swamy, M.N.S., "High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers," Computer Modelling and Simulation (UKSim),2012 UKSim 14th International Conference on , vol., no.,pp.649,654, 28-30 March 2012.
[9] Begum JT, Naidu HS, Vaishnavi N, Sakana G, Prabhakaran N. Design and Implementation of Reconfigurable ALU for Signal Processing Applications. Indian Journal of Science and Technology. 2016 Jan; 9(2):1–6. DOI: 10.17485/ ijst/2016/v9i2/86343.
[10] Nandal A, Vigneswaran T, Rana AT. Booth multiplier using reversible logic with low power and reduced logical complexity. Indian Journal of Science and Technology. 2014 Jan; 7(4):525–29. DOI: 10.17485/ijst/2014/v7i4/48644
[11] C. P. Narendra ; K. M. Ravi Kumar, “Low power compressor based MAC architecture for DSP applicationsâ€, International Conference on Circuits, Communication, Control and Computing Year: 2014.
-
Downloads
-
How to Cite
Rahul Reddy, P., Vyomal N, P., & Choubey, A. (2018). An Efficient MAC Architecture using Multiplier for DSP and DIP Operations. International Journal of Engineering & Technology, 7(2.16), 110-113. https://doi.org/10.14419/ijet.v7i2.16.11505Received date: 2018-04-13
Accepted date: 2018-04-13
Published date: 2018-04-12