Latency and throughput analysis of a pipelined GDI ripple carry adder

  • Abstract
  • Keywords
  • References
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  • Abstract

    Latency and Throughput are deemed parameters of prime importance that determine the speed of an Adder Circuit. Ongoing research in the field of Digital Signal Processing involves optimizing an Adder regarding these parameters. This article picks up the study of a ripple carry adder and presents the use of two methods towards ameliorating the performance of an adder – viz., the use of GDI (Gate Diffusion Input) technology for reduced Latency, and implementation of a pipelined architecture towards increasing the throughput. In this paper, we have dileneated the function of a basic GDI cell, with which a 1-bit ripple carry full adder was designed, which in turn formed the basic building blocks of 8-bit and 32-bit ripple carry adders. These full adders were designed using GDI technology while employing the concept of pipelining resulting in a novel structure optimizing both latency and throughput. This paper also presents a comparison among CMOS and GDI RCAs of 8 and 32bits with and without pipelining.

    On simulating 32-bit RCAs in Cadence virtuoso tool using gpdk 180nm technology ,those with pipelining had a 4.5 times increase in throughput with 42.8% increase in latency.


  • Keywords

    Latency, throughput, digital signal processing, ripple carry adder, GDI, pipeline.

  • References

      [1] Krishnendu D, “Design of a Low Power, High Speed, Energy Efficient Full Using Modified GDI and MVT Scheme in 45nm Technology”, International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), (2014).

      [2] Jubal S & Shoaib K, “A Low Power Variable Sized CSLA Implementation Using GDI Logic In 45nm SOI Technology”, IEEE 1st International Conference on Next Generation Computing Technologies, (2015).

      [3] Biswarup M & Aniruddha G, “Design &Study of a Low Power High Speed Full Adder Using GDI Multiplexer”, IEEE 2nd International Conference on Recent Trends in Information Systems, (2015).

      [4] Shoba M & Nakkeeran R, “Performance Analysis of 1 bit Full Using GDI Logic”, IEEE ICICES2014 - S.A. Engineering College, Chennai, Tamil Nadu, India, (2014).

      [5] Lin CH & Wu AY, “Algorithm and Architecture for High-Performance Vector Rotational DSP Applications”, Regular IEEE Transactions: Circuits and Systems I, Vol.52, (2005), pp.2385- 2398.

      [6] Vitoroulis K & Al-Khalili AJ, “Performance of Parallel Prefix Adders Implemented with FPGA technology”, IEEE Northeast Workshop on Circuits and Systems, (2007), pp.498-501.

      [7] Aniruddha G & Biswarup M, “Design &study of a low power high speed full adder using GDI multiplexer”, IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS), (2015), pp.465 – 470.

      [8] Shoba M & Nakkeeran R, “Performance analysis of 1 bit full adder using GDI logic”, International Conference on Information Communication and Embedded Systems (ICICES), (2014), pp.1 – 4.

      [9] Anitesh S & Ravi T, “Low power 8-bit ALU design using full adder and multiplexer”, International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), (2016), pp.2160 – 2164.

      [10] Rashmi DS, SadiyaRukhsar R, Shilpa HR, Vidyashree CR, Kunjan DS & Nithin HV, “Modeling of adders using CMOS and GDI logic for multiplier applications: A VLSI based approach”, International Conference on Circuit, Power and Computing Technologies(ICCPCT), (2016), pp.1 – 6.

      [11] Sujatha H & Deepali K, “Low power full adder circuit using Gate Diffusion Input (GDI) MUX”, Fourth International Conference on Communication and Computing, (2012), pp.53 – 56.

      [12] Hoe DHK, Martinez C & Vundavalli J, “Design and Characterization of Parallel Prefix Adders using FPGAs”, IEEE 43rd Southeastern Symposium on System Theory, (2011), pp.170- 174.

      [13] Choi Y, “Parallel Prefix Adder Design”, Proc. 17th IEEE Symposium on Computer Arithmetic, (2005), pp. 90-98.

      [14] Chang L, Fei Q, Xinghua Y & Huazhong Y, “Hardware acceleration with pipelined adder for Support Vector Machine classifier”, Fourth International Conference on Digital Information and Communication Technology and it's Applications (DICTAP), (2014), pp.13 – 16.




Article ID: 11848
DOI: 10.14419/ijet.v7i2.21.11848

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