Complex Number Vedic Multiplier and its Implementation in a Filter

  • Authors

    • N Saraswathi
    • Lokesh Modi
    • Aatish Nair
    2018-04-25
    https://doi.org/10.14419/ijet.v7i2.24.12078
  • Ancient Indian Mathematics, Urdhva Tiryakbhyam Sutra, Real vedic Multiplier, Complex number multiplication, FIR filter

  • Abstract

    Complex numbers multiplication is a fundamental mathematical process in systems like digital signal processors (DSP). The main     objective of complex number multiplication is to perform operations at lightning fast speed with less intake of power. In this paper, the best possible architecture is designed for a Real vedic multiplier based on the ancient Indian mathematical procedure known as URDHVA TIRYAKBHYAM SUTRA i.e. the structure of a MxM Vedic real multiplier architecture is developed. Then, a Vedic real multiplier solution of a complex multiplier is presented and its simulation results are obtained. The MxM Vedic real multiplier architecture, architecture of the Real Vedic  multiplier solution for 32 x 32 bit complex numbers multiplication of complex multiplier and the architecture of a FIR filter has been code in Verilog and implementation is done through Modelsim 5.6 and Xilinx ISE 7.1 navigator.

     

  • References

    1. [1] K Deergha Rao, Ch. Gnagdhar, FPGA Implementation Of Com-plex Multiplier Using Minimum delay Vedic Real Multiplier Archi-tecture, Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON), Indian Institute of Technology (Banaras Hindu University), Varanasi, India, Dec9-11, IEEE-2016

      [2] Sudeep M.C., M. Sharath Bimb, Mahendra Vucha, “Design and FPGA Implementation of High Speed Vedic Multiplierâ€, Interna-tional Journal of Computer Applications (0975 – 8887)Volume 90 – No 16, March 2014

      [3] P. K. Saha, A. Banerjee, and A. Dandapat, "High Speed Low Power Complex Multiplier Design Using Parallel Adders and Sub-tractors," International Journal on Electronic and Electrical Engineer-ing, (IJEEE), vol 07, no. II, pp 38-46, Dec. 2011.

      [4] Tiwari, H. D, Gankhuyag, G., Kim, C. M., and Cho, Y. B. "Mul-tiplier design based on ancient Indian Vedic Mathematics,"Proc. IEEE International SoC Design Conference (ISOCC’08), Vol.2, pp.65-68, 2008.

      [5] Agadguru Swami Sri Bharath, Krsna Tirathji, "Vedic Mathemat-ics or Sixteen Simple Sutras From The Vedas", Motilal Banarsidas, Varanasi (India),1986.

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  • How to Cite

    Saraswathi, N., Modi, L., & Nair, A. (2018). Complex Number Vedic Multiplier and its Implementation in a Filter. International Journal of Engineering & Technology, 7(2.24), 336-340. https://doi.org/10.14419/ijet.v7i2.24.12078

    Received date: 2018-04-24

    Accepted date: 2018-04-24

    Published date: 2018-04-25