Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

  • Authors

    • Srinath B
    • P Aruna priya
    • Chirag Kasliwal
    2018-04-25
    https://doi.org/10.14419/ijet.v7i2.24.12145
  • Electron migration, Floorplanning, Low power Integrated Circuits (ICs), Multiple Supply Voltage (MSV), Voltage drop.

  • Abstract

    In Contemporary Integrated Circuits (IC), the Voltage drop in the power rails and Electron migration risk (EM) due to high current densities are the most important factors degrading the reliability of the chip. The effect of these factors leads to an imbalance in the flow of charge carriers and voids in interconnects. This paper resolves the above issues, through analyzing and predetermining it in a Multiple Supply Voltage (MSV) design during the floorplanning stage. Simulations were carried out in Cadence digital Encounter system with 180nm technology for the circuit net list of 8 point FFT (Fast Fourier Transform) and FIR filter. Results show that floorplanning scheme is powerful in reducing 100% of voltage drop and 50% of EM risk in the chip as compared to previous works.

     

     

  • References

    1. [1] Q. Zhou, J. Shi, B. Liu, and Y. Cai, “Floorplanning considering ir drop in multiple supply voltages island designs,†IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 638–646, 2011.

      [2] D. Sengupta, A. Veneris, S.Wilton, A. Ivanov, and R. Saleh, “Sequence pair based voltage island floorplanning,†International Green Computing Conference and Workshops, pp. 1–6, 2011.

      [3] W. p. Lee, H. y. Liu, and Y. w. Chang, “Voltage island aware floorplanning for power and timing optimization,†in 2006 IEEE/ACM International Conference on Computer Aided Design, pp. 389–394, Nov 2006.

      [4] J. R. Black, “Electromigrationa brief survey and some recent results,†IEEE Transactions on Electron Devices, vol. 16, no. 4, pp. 338–347, 1969.

      [5] D. E. Khalil and Y. Ismail, “Optimum sizing of power grids for ir drop,†in 2006 IEEE International Symposium on Circuits and Systems, pp. 4 pp.–484, May 2006.

      [6] J. Lienig and G. Jerke, “Electromigration-aware physical design of integrated circuits,†in 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, pp. 77–82, Jan 2005.

      [7] T. Lu, Z. Yang, and A. Srivastava, “Electromigration-aware placement for 3d-ics,†in 2016 17th International Symposium on Quality Electronic Design (ISQED), pp. 35–40, March 2016.

      [8] R. Martins, R. P´ovoa, N. Lourenc¸o, and N. Horta, “Current-flow and current-density-aware multi-objective optimization of analog fICg placement,†Integration, the fVLSIg Journal, vol. 55, pp. 295 – 306, 2016.

      [9] J.-M. Lin and Z.-X. Hung, “Skb-tree: A fixed-outline driven representation for modern floorplanning problems,†IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 3, pp. 473–484, 2012.

      [10] Q. Ma and E. F. Y. Young, “Multivoltage floorplan design,†IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 607–617, April 2010.

      [11] D. Sengupta, A. Veneris, S.Wilton, A. Ivanov, and R. Saleh, “Squence pair based voltage island floorplanning,†in 2011 International Green Computing Conference and Workshops, pp. 1–6, July 2011.

      [12] A. Todri, S. C. Chang, and M. Marek-Sadowska, “Electromigration and voltage drop aware power grid optimization for power gated ics,†in Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on, pp. 391–394, Aug 2007.

      [13] S.V.Manikanthan and T.Padmapriya “Recent Trends In M2m Communications In 4g Networks And Evolution Towards 5gâ€, International Journal of Pure and Applied Mathematics, ISSN NO: 1314-3395, Vol-115, Issue -8, Sep 2017.

      [14] S.V. Manikanthan, T. Padmapriya “An enhanced distributed evolved node-b architecture in 5G tele-communications network†International Journal of Engineering & Technology (UAE), Vol 7 Issues No (2.8) (2018) 248-254.March2018.

      [15] S.V. Manikanthan, T. Padmapriya, Relay Based Architecture For Energy Perceptive For Mobile Adhoc Networks, Advances and Applications in Mathematical Sciences, Volume 17, Issue 1, November 2017, Pages 165-179

  • Downloads

  • How to Cite

    B, S., Aruna priya, P., & Kasliwal, C. (2018). Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk. International Journal of Engineering & Technology, 7(2.24), 496-499. https://doi.org/10.14419/ijet.v7i2.24.12145

    Received date: 2018-04-25

    Accepted date: 2018-04-25

    Published date: 2018-04-25