Design of High Performance Decoder with Mixed Logic Styles

  • Authors

    • Mohammad Khadir
    • S Renukarani
    • Tunikipati Usharani
    • D Hemanth Kumar
    2018-04-18
    https://doi.org/10.14419/ijet.v7i2.20.12187
  • Logic gates, Line Decoder, Cadence

  • Abstract

    The CMOS technology is the mostly portable technology used in the designing of the circuits and in its fabrication. Designing of the circuits using CMOS technology requires the high power, high transistors count and low performance. The basic idea of the project is in order to reduce the count of transistors, time delay, and power consumption and to increase the performance of the circuits such as line decoders. The line decoder is a combinational circuits to which „n‟ no .of inputs are given as input and the output is 2^n based on the selected input and it requires 20 and more than 20 transistors to design any MxN decoders using CMOS technology .In order to configure the parameters and to make it more portable we are using different types of logic styles this usage of technologies more than one technologies on each circuit is a mixed logic styles .In this concept we observe the results as per required .The technologies we use in this is TGL/DVL. The suggested framework “Design about low Power, helter execution 2-4 What's more 4-16 blended rationale offering Decoders†is executed done 45nm engineering utilizing cadence virtuoso tool. The circuit schematic is designed and the circuits are simulated for functionality verification.

     

     

  • References

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      [2] R. Zimmermann and W.Fichtner, “Low-Power Logic Styles: CMOS Versus Pass- Transistor Logic,†IEEE Journal of Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, 1997.

      [3] K. Yano, et al., “A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic,†IEEE J. Solid-State Circuits, vol. 25, pp. 388-393,1990.

      [4] M. Suzuki, et al., “A 1.5ns 32b CMOS ALU in double pass-transistor logic,†Proc. 1993 IEEE Int. Solid-State Circuits Conf., pp.90-91,1993.

      [5] X. Wu, “Theory of transmission switches and its application to design of CMOS digital circuits,†International J. Circuit Theory and Application, vol. 20, no. 4, pp. 349-356,1992.

      [6] V. G. Oklobdzija and B. Duchene, “Pass-transistor dual value logicfor low-power CMOS,†Proc. of the Int. Symp. on VLSI Technology, pp. 341-344,1995.

      [7] M. A.Turi and J.G. Delgado-Frias, “Decreasing energy consumption in address decoders by means of selective precharge schemes,†Microelectronics Journal, vol. 40, no. 11, pp.1590- 1600, 2009.

      [8] V. Bhatnagar, A. Chandani and S. Pandey, “Optimization of row decoder for 128×128 6T SRAMs,†2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), pp. 1-4,2015.

      [9] A. K. Mishra, D. P. Acharya and P. K. Patra, “Novel design technique of address Decoder for SRAM,†2014 International Conference on Advanced Communication Control and Computing Technologies (ICACCCT), pp. 1032-1035,2014.

      [10] D. Mar ovi , B. Ni oli and V. O lobdi a, “A general method in synthesis of pass-transistor circuits,†Microelectronics Journal, vol 31, pp. 991-998,2000.

      [11] N. Lotze and Y. Manoli, “A 62mV 0.13μm CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic,†IEEE Journal of Solid State Circuits, vol. 47, no.1, pp. 47- 60, Jan. 2012.

      [12] N. H. E. Weste and D. M. Harris, “CMOS VLSI Design, a Circuits and Systems Perspective,†4th ed., 2011: Addison-Wesley.

      [13] R. Zimmermann and W.Fichtner, “Low-Power Logic Styles: CMOS Versus Pass- Transistor Logic,†IEEE Journal of Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, 1997.

      [14] K. Yano, et al., “A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic,†IEEE J. Solid-State Circuits, vol. 25, pp. 388-393,1990.

      [15] M. Suzuki, et al., “A 1.5ns 32b CMOS ALU in double pass-transistor logic,†Proc. 1993 IEEE Int. Solid-State Circuits Conf., pp.90-91,1993.

      [16] X. Wu, “Theory of transmission switches and its application to design of CMOS digital circuits,†International J. Circuit Theory and Application, vol. 20, no. 4, pp. 349-356,1992.

      [17] V. G. Oklobdzija and B. Duchene, “Pass-transistor dual value logicfor low-power CMOS,†Proc. of the Int. Symp. on VLSI Technology, pp. 341-344,1995.

      [18] M. A.Turi and J.G. Delgado-Frias, “Decreasing energy consumption in address decoders by means of selective precharge schemes,†Microelectronics Journal, vol. 40, no. 11, pp.1590- 1600, 2009.

      [19] V. Bhatnagar, A. Chandani and S. Pandey, “Optimization of row decoder for 128×128 6T SRAMs,†2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), pp. 1-4,2015.

      [20] A. K. Mishra, D. P. Acharya and P. K. Patra, “Novel design technique of address Decoder for SRAM,†2014 International Conference on Advanced Communication Control and Computing Technologies (ICACCCT), pp. 1032-1035,2014.

      [21] D. Mar ovi , B. Ni oli and V. O lobdi a, “A general method in synthesis of pass-transistor circuits,†Microelectronics Journal, vol 31, pp. 991-998,2000.

      [22] N. Lotze and Y. Manoli, “A 62mV 0.13μm CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic,†IEEE Journal of Solid State Circuits, vol. 47, no.1, pp. 47- 60, Jan. 2012.

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  • How to Cite

    Khadir, M., Renukarani, S., Usharani, T., & Hemanth Kumar, D. (2018). Design of High Performance Decoder with Mixed Logic Styles. International Journal of Engineering & Technology, 7(2.20), 119-123. https://doi.org/10.14419/ijet.v7i2.20.12187

    Received date: 2018-04-26

    Accepted date: 2018-04-26

    Published date: 2018-04-18