Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications

  • Authors

    • Umesh Dutta MANAV RACHNA INTERNATIONAL INSTITUTE OF RESEARCH & STUDIES
    • M K. Soni MANAV RACHNA INTERNATIONAL INSTITUTE OF RESEARCH & STUDIES
    • Manisha Pattanaik ABV-IIITM Gwalior
    2018-09-17
    https://doi.org/10.14419/ijet.v7i4.12352
  • TFET, Technology Computer-Aided Design Simulation (TCAD), Band to Band Tunneling (BTBT), Subthreshold Slope, High-K Dielectric, Am bipolar Current.

  • Abstract

    This paper investigates the performance of tri material gate tunnel field effect transistor (TMGTFET) device designed in gate all around (GAA) configuration. The device performance is analyzed by varying various device related parameters like: drain doping, oxide thickness and radius of silicon core. Simulations are performed using technology computer-aided design (TCAD) tool at 60 nm gate length. Simulation results show that the performance of TMGTFET device can be optimized by proper selection of device parameters so as to achieve improvements in the ON current, OFF current, sub-threshold swing and ambipolar current. The silicon based TMGTFET device demonstrates good performance which makes it a suitable candidate for low power applications with ON current of 0.386 µA/µm, average sub-threshold swing of 32.06 mV/decade, maximum current gain cut off frequency of 41.4 GHz and extremely low OFF current value of the order of 10-20A/µm. We have performed the device optimization to boost the ON current and improve the sub-threshold slope in order to make sure that this device configuration becomes suitable for both low power and high performance applications. The proposed hetero dielectric tri material gate tunnel FET device (HD-TFET) designed in gate all around configuration achieves 19.7 times improvement in ON current as compared to TMGTFET device and excellent average sub-threshold swing of 21.2 mV/decade. The maximum unity current gain frequency is also improved by 3 times indicating its potential for deployment in high frequency applications.

     

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  • How to Cite

    Dutta, U., K. Soni, M., & Pattanaik, M. (2018). Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications. International Journal of Engineering & Technology, 7(4), 2263-2270. https://doi.org/10.14419/ijet.v7i4.12352

    Received date: 2018-05-03

    Accepted date: 2018-08-25

    Published date: 2018-09-17