A genetic algorithm approach for global routing of VLSI circuits

  • Authors

    • D Ravikumar
    • Arun Raaza
    • V Devi
    • E Gopinathan
    2018-04-20
    https://doi.org/10.14419/ijet.v7i2.21.12450
  • Very Large Scale Integrating (VLSI), Genetic Algorithm (GA), routing, Macro cell, placer, graph edges.

  • Abstract

    Very Large Scale Integrating (VLSI) design has the objectives of producing the layout for integrating circuits. The currently prevalent submicron regions require innovative, new physical design algorithms. Performance requirements have not seen before, become the significant features of such regions. The last ten years have been witnessing the feature of swelling success of Genetic Algorithms in their application to VLSI physical design. These algorithms are in spot light and the subject matter of study and examination. Routing problem is posed to a cost function which takes care of the total net length, the channel capacity exceedance and crosstalk. The Genetic algorithm is used for optimizing the cost function.

     

     

  • References

    1. [1] Abdel E & Nagarajan R, “Multi terminal Net Routing for partial Cross bar–Based Multi FPGA systemsâ€, IEEE Trans. on VLSI systems, Vol.11, No.1, (2003).

      [2] Abdel E & Ranganathan N, “Routing on Field Programmable switch matricesâ€, IEEE Trans. on VLSI systems, Vol.11, No.2, (2003), pp.283 – 287.

      [3] Palesi M, Holsmark R, Kumar S & Catania V, “Application Specific Routing Algorithms for Networks on Chipâ€, IEEE Transactions on Parallel and Distributed Systems, Vol.20, No.3, (2009), pp.316–330.

      [4] James C, John K, & Jens K, “Evolutionary algorithms for Physical Design of VLSI Circuitsâ€, Advances in Evolutionary Computing, Theory and Applications, Springer Verlag, London, (2003), pp. 683-712.

      [5] Jinjun X & Lei H, “Extended Global Routing with RLC Cross talk Constraintsâ€, IEEE Trans. on VLSI systems, Vol.13, No.3, (2005), pp.319 – 328.

      [6] Michael JSS, “Application Specific Integrated Circuitsâ€, Pearson Education Singapore Pte. Ltd., (2002).

      [7] Pinaki M & Elizabeth MR, “Genetic Algorithms for VLSI Design, Layout and Test Automationâ€, Addison Wesley Singapore Pte Ltd, (1999).

      [8] Krishan KP, Jinesh SG, Navaneeth R, Vijay L & Gaur Vijay, “Implementation of qos aware q-routing algorithm for network-on-hipâ€, Communications in Computer and Information Science, Vol.40, (2009), pp.370–380.

      [9] Srinivas B & Farid N, “Pre layout Estimation of individual Wire Lengthsâ€, IEEE Trans. on VLSI systems, Vol.9, No.6, (2001), pp.943 – 958.

      [10] Dong X & Kele S, “A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testingâ€, ACM Transactions on Design Automation of Electronic Systems, Vol.21, No.2, (2016).

      [11] Deivakani M & Shanthi D, “Design of Efficient Router with Low Power and Low Latency for Network on Chipâ€, Circuits and Systems, Vol.7, No.4, (2016), pp.339–349.

      [12] Hameem Shanavas I & Gnanamurthy RK, “Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithmâ€, Mathematical Problems in Engineering, (2014), pp.1–15.

      [13] Angelo KL & Jean L, “A SDM-TDM-based circuit-switched router for on-chip networksâ€, ACM Transaction on Reconfigurable Technology &Systems, Vol.5, No. 3, (2012).

      [14] Radu S & Kees G, “Multi-path routing in time-division-multiplexed networks on chipâ€, Proceedings 17th IFIP International Conference on VLSI-SoC, (2009), pp.109–114.

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  • How to Cite

    Ravikumar, D., Raaza, A., Devi, V., & Gopinathan, E. (2018). A genetic algorithm approach for global routing of VLSI circuits. International Journal of Engineering & Technology, 7(2.21), 394-397. https://doi.org/10.14419/ijet.v7i2.21.12450

    Received date: 2018-05-04

    Accepted date: 2018-05-04

    Published date: 2018-04-20