FPGA-based redundancy bits reduction algorithm using the enhanced error detection correction code

  • Authors

    • Lean Karlo TOLENTINO Technological University of the Philippines
    • Maria Victoria PADILLA Technological University of the Philippines
    • Ronnie SERFA JUAN Technological University of the Philippines
    2018-06-23
    https://doi.org/10.14419/ijet.v7i3.12681
  • Cyclic Redundancy Check, Data Communication, Error Correction, Field Programmable Gate Arrays, Parity Check Codes.

  • Abstract

    To ensure an error-free transmission in packet switching, additional check bits (either header or a payload) are typically appended to the input data of a message for error detection especially in a string of binary code. Normally, it comes from the input message and as a result of a deterministic algorithm after these data have been processed. The receiver system implements the said algorithm, while the transmitter used it to match the reliability of the sent information and detects whether an error bit has occurred or not. The corrupted bits will be corrected, recovered, and matched with the original message. To further improve the detection and correction of the corrupted transmitted bits, an enhanced error detection correction code implementation was proposed and developed in this paper. This will improve the limitations of using cyclic redundancy checking (CRC) code and Hamming code, by reducing the number of the redundancy bits ‘r’ in CRC due to the needed polynomial generator, and the overhead of interspersing of the r in conventional Hamming code, respectively. Xilinx Spartan 6 (XC7Z020-2CLG4841) FPGA was used to synthesize the proposed enhanced error detection code (EEDC) method. Based on the results, the transmission rate is faster, and an increase in detection of random errors compared with using CRC and Hamming codes.

     

     

  • References

    1. [1] Kurose JF & Ross KW (2012), “Computer networking: a top-down approachâ€, Pearson, pp. 36-44.

      [2] Leon-Garcia A & Widjaja I (2003), “Communication networks,†McGraw-Hill, Inc. pp. 101-105.

      [3] Baker RP (1998), “Computer assisted survey information collection,†Vol. 66, John Wiley & Sons, pp. 320-321.

      [4] Ullah S, Khan J, Latif S, & Ullah I (2011), “Indication of Efficient Technique for Detection of Check Bits in Hamming Codeâ€, International Journal of Computer Science Issues, Vol. 8, No. 5, pp. 241-246.

      [5] Wu J, Liu H, Dobre OA, Fang C, & Qian L (2013), “CA-MAC: A Novel MAC Protocol to Alleviate Congestion in Wireless Sensor Networks,†Advances in Electrical and Computer Engineering, Vol. 13, No. 4, pp. 41-46. https://doi.org/10.4316/AECE.2013.04007.

      [6] Poudyal N, Lee HC, Kwon YJ, & Lee BS (2011), “Delay-bound Admission Control for Real-time Traffic in Fourth Generation IMT-Advanced Networks based on 802.16m,†Advances in Electrical and Computer Engineering, Vol. 11, No. 1, pp. 31-38. https://doi.org/10.4316/AECE.2011.01005.

      [7] Chen CL, Lai YL, Chen CC, & Chen KC (2009), “Construction of a Real-Time and Secure Mobile Ticket System,†Journal of Information Science & Engineering, Vol. 25, No. 3, pp. 807-825.

      [8] Beck MT & Linnhoff-Popien C (2014), “On delay-aware embedding of virtual networks,†Proceedings of the AFIN 2014: The sixth international conference on advances in future internet, Lisbon, Portugal, pp. 55-59.

      [9] Venkataram P, Chaudhari S, Rajavelsamy R, Ramamohan TR, & Ramakrishna H (2004), “Disk-oriented VCR operations for a multiuser VOD system,†Journal of the Indian Institute of Science, Vol. 84, No. 5, pp. 123-140.

      [10] Irvin IR (2003), “Cyclic redundancy checks with factorable generators,†IEE Proceedings – Communications, Vol. 150, No. 1, pp. 17-20. https://doi.org/10.1049/ip-com:20030189.

      [11] Park SI & Yang KC (2002), “Extended Hamming accumulate codes and modified irregular repeat accumulate codes,†Electronics Letters, Vol. 3, No. 10, pp. 467 – 468. https://doi.org/10.1049/el:20020316.

      [12] Kora P (2017), “Single Bit Error Detection and Correction using Novel Hamming Code Methodâ€, Imperial Journal of Interdisciplinary Research, Vol. 3, No. 1, pp. 1285-1288.

      [13] Gad VR, Gad RS, & Naik GM (2015), “Configurable CRC Error Detection Model for Performance Analysis of Polynomial: Case Study for the 32-Bits Ethernet Protocolâ€, Lecture Notes in Computer Science, Vol. 9247, pp. 529-542. https://doi.org/10.1007/978-3-319-23126-6_46.

      [14] Singh S, Sujana S, Babu I, & Latha K (2013), “VLSI Implementation of Parallel CRC using Pipelining, Unfolding and Retimingâ€, IOSR Journal of VLSI and Signal Processing (IOSR-JSVP), Vol. 2, No. 5, pp. 67-72.

      [15] Koopman P & Chakravarty T (2004), “Cyclic redundancy code (CRC) polynomial selection for embedded networks,†Proceedings of the 2004 International Conference on Dependable Systems and Networks, Florence, Italy, pp. 145-154. https://doi.org/10.1109/DSN.2004.1311885.

      [16] Serfa Juan RO & Kim HS (2018), “Implementation of EEDC for Trailer Segment in Enhanced FPGA-based FlexRay Controller,†Journal of Telecommunication, Electronic and Computer Engineering (JTEC), Vol. 10, No. 1-9, pp. 161-166.

      [17] Serfa Juan RO, Jeong MW, Kim HS (2016). “Development of burst error effect reduction algorithm for CAN using interleaver method,†2016 International SoC Design Conference (ISOCC), Jeju, South Korea, pp. 165-166. https://doi.org/10.1109/ISOCC.2016.7799843.

      [18] Muthiah D & Raj AAB (2012), “Implementation of high-speed LFSR design with parallel architectures,†Proceedings of the 2012 International Conference on Computing, Communication and Applications (ICCA), Tamilnadu, India, pp. 1-6. https://doi.org/10.1109/ICCCA.2012.6179137.

      [19] Bertozzi D, Benini L, & De Micheli G (2005), “Error control schemes for on-chip communication links: the energy-reliability tradeoff,†IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 818-831. https://doi.org/10.1109/TCAD.2005.847907.

      [20] Tomasi W (2014), “Advanced Electronic Communications Systems,†6th edition, Pearson, pp. 161-168.

      [21] Forouzan BA (2013), “Data communications & networking,†McGraw-Hill, pp. 257-273.

      [22] Noorbasha F & Suresh K (2018). “FPGA implementation of RGB image encryption and decryption using DNA cryptographyâ€. International Journal of Engineering & Technology, Vol. 7, No. 2.8, pp. 397-403. https://doi.org/10.14419/ijet.v7i2.8.10469.

      [23] Nasaruddin N, Yuhanda B, Elizar E, & Syahrial S (2017), “Design and Performance Analysis of Channel Coding Scheme based on Multiplication by Alphabet-9,†Journal of Telecommunication, Electronic and Computer Engineering (JTEC), Vol. 9, No. 1, pp. 7-13.

      [24] Bulo Y, Anju M, & Bhunia CT (2016), “Implementing (7, 4) Hamming Code with Extra One Parity Bit and Bit Reverse Scheme To Correct Errors At The Receiver Side,†International Journal of Applied Engineering Research, Vol. 11, No. 1, pp. 22-27.

      [25] Bucur IG, Stanescu D, & Stratulat M (2013), “Enhanced Segment Compression Steganographic Algorithm,†Advances in Electrical and Computer Engineering, Vol. 13, No. 3, pp. 101-106. https://doi.org/10.4316/AECE.2013.03016.

      [26] Sanchez-Macian A, Reviriego P, & Maestro JA (2012), “Enhanced detection of double and triple adjacent errors in hamming codes through selective bit placement,†IEEE Transactions on Device and Materials Reliability, Vol. 12, No. 2, pp. 357-362. https://doi.org/10.1109/TDMR.2012.2186965.

      [27] Sedcole P, Blodget B, Becker T, Anderson J, & Lysaght P (2006), “Modular dynamic reconfiguration in Virtex FPGAs,†IEE Proceedings-Computers and Digital Techniques, Vol. 153, No. 3, pp. 157-164. https://doi.org/10.1049/ip-cdt:20050176.

      [28] Serfa Juan RO & Kim HS (2018), “Reconfiguration of an FPGA-Based Time-Triggered FlexRay Network Controller using EEDC,†Journal of Circuits, Systems, and Computers, Vol. 27, No. 6, pp. 1-11. https://doi.org/10.1142/S0218126618500962.

      [29] Brekhov O & Ratnikov M (2014), “Pipelined Error-detecting Codes in FPGA Testing,†Advances in Electrical and Computer Engineering, Vol. 14, No. 2, pp. 57-62. https://doi.org/10.4316/AECE.2014.02010.

      [30] Serfa Juan RO & Kim HS (2016), “Using DSP Algorithms for CRC in a CAN Controller,†IEIE Transactions on Smart Processing & Computing, Vol. 5, No. 1, pp. 29-34. https://doi.org/10.5573/IEIESPC.2016.5.1.29.

      [31] Tolentino LKS & Beleno DMT (2017), “Development of a 3D Disparity Estimation Processing Architecture,†International Journal of Applied Engineering Research. Vol. 12, No. 19, pp. 8420-8424.

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  • How to Cite

    TOLENTINO, L. K., PADILLA, M. V., & SERFA JUAN, R. (2018). FPGA-based redundancy bits reduction algorithm using the enhanced error detection correction code. International Journal of Engineering & Technology, 7(3), 1008-1013. https://doi.org/10.14419/ijet.v7i3.12681

    Received date: 2018-05-10

    Accepted date: 2018-06-01

    Published date: 2018-06-23