Design of low power and high speed implicit pulse flip-flop and its application

  • Authors

    • Kuruvilla John Noorul Islam Centre for Higher Education.
    • Vinod Kumar R S Noorul Islam Centre for Higher Education.
    • Kumar S S Noorul Islam Centre for Higher Education.
    2018-08-23
    https://doi.org/10.14419/ijet.v7i3.12845
  • High Speed, Implicit, Low Power, Pulse Flip-Flops, Signal Feed-Through.

  • Abstract

    In this paper, a new power efficient and high speed pulsed-triggered flip-flop in implicit style with conditional pulse enhancement and signal feed-through (CPESFTFF) is proposed. This novel architecture is presented for the pulse-triggered D-FF in the CMOS 90-nm technology. Two important features are embedded in this flip-flop architecture. Firstly, a conditional enhancement in width and height of the triggering pulses by using an additional pMOS transistor in the structure is done. Secondly, a modified signal feed-through mechanism which directly samples the input to output by using an nMOS pass transistor is introduced. The proposed design achieves better speed and power performance by successfully solving the longest discharging path problem. The simulation results show that the proposed architecture has improvement in terms of power consumption, D-to-Q delay, and Power Delay Product Performance (PDP) in comparison with other conventional P-FF architectures. A 3-bit up counter is also implemented using proposed P-FF.

     

     

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  • How to Cite

    John, K., Kumar R S, V., & S S, K. (2018). Design of low power and high speed implicit pulse flip-flop and its application. International Journal of Engineering & Technology, 7(3), 1893-1898. https://doi.org/10.14419/ijet.v7i3.12845

    Received date: 2018-05-15

    Accepted date: 2018-06-08

    Published date: 2018-08-23