Enhanced compaction and reordering procedure for transition fault testing
-
2018-11-14 https://doi.org/10.14419/ijet.v7i4.13249 -
Average Switching Activity, Broadside Tests, Reordering, Skewed-Load Tests, Static Test Compaction, Test Cubes, Transition Faults. -
Abstract
Compaction procedure, used to reduce test power, can be efficiently applied on test cubes or incompletely specified tests. This paper demonstrates an improved static compaction and switching activity based test vector reordering methodology which can be applied on a test set that contains both skewed load and broadside tests for transition faults. This compaction procedure goes beyond the normal test vector merging approach generally employed in testing circuits. Here a test is combined with several other tests even if they are not compatible. After obtaining a compact test set, the vectors are reordered such that the total switching activity of the circuit including all the internal nodes is reduced. The simulation results show a considerable reduction in the number of tests and as the test volume reduces the test power also decreases. An average 28.6% reduction in number of test vector pairs is observed as compared to existing static compaction methods and 30.6% reduction in average switching activity (ASA) after reordering.
Â
Â
 -
References
[1] Pomeranz, I. (2013). On test compaction of broadside and skewed-load test cubes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(9), 1705-1714. https://doi.org/10.1109/TVLSI.2012.2217360.
[2] Ang, C. H. (2013, November). Single Test Clock with Programmable Clock Enable Constraints for Multi-clock Domain SoC ATPG Testing. In Test Symposium (ATS), 2013 22nd Asian (pp. 195-200). IEEE.
[3] Saeed, S. M., & Sinanoglu, O. (2014). Design for testability support for launch and capture power reduction in launch-off-shift and launch-off-capture testing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(3), 516-521. https://doi.org/10.1109/TVLSI.2013.2248764.
[4] Mohan, N., & Anita, J. P. (2016). A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults. International Journal of Mathematical Modelling and Numerical Optimisation, 7(1), 83-96. https://doi.org/10.1504/IJMMNO.2016.074374.
[5] Pomeranz, I. (2011, May). Static test compaction for delay fault test sets consisting of broadside and skewed-load tests. In VLSI Test Symposium (VTS), 2011 IEEE 29th (pp. 84-89). IEEE. https://doi.org/10.1109/VTS.2011.5783760.
[6] Pomeranz, I., & Reddy, S. M. (2011). Static Test Data Volume Reduction Using Complementation or Modulo-$ M $ Addition. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(6), 1108-1112. https://doi.org/10.1109/TVLSI.2010.2044819.
[7] Mohan, N., Krishnan, M., Rai, S. K., MathuMeitha, M., & Sivakalyan, S. (2017, September). Efficient test scheduling for reusable BIST in 3D stacked ICs. In Advances in Computing, Communications and Informatics (ICACCI), 2017 International Conference on (pp. 1349-1355). IEEE.
[8] Pomeranz, I. (2016). Static test compaction for circuits with multiple independent scan chains. IET Computers & Digital Techniques, 10(1), 12-17. https://doi.org/10.1049/iet-cdt.2014.0191.
[9] Naeini, M. M., Dass, S. B., Ooi, C. Y., Yoneda, T., & Inoue, M. (2017). An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. Integration, the VLSI Journal, 57, 108-124. https://doi.org/10.1016/j.vlsi.2016.12.009.
-
Downloads
-
How to Cite
Mohan, N., & P. Anita, J. (2018). Enhanced compaction and reordering procedure for transition fault testing. International Journal of Engineering & Technology, 7(4), 4357-4361. https://doi.org/10.14419/ijet.v7i4.13249Received date: 2018-05-24
Accepted date: 2018-08-22
Published date: 2018-11-14