Implementation of various data encryption methods for medical information transmission

  • Authors

    • S Neelima
    • R Brinda
    2018-05-29
    https://doi.org/10.14419/ijet.v7i2.31.13446
  • RSA, AES, DES, SHA, encryption, decryption, FPGA, power consumption, delay, area

  • Abstract

    Encryption is the process of converting the data from readable format into unreadable format with help of any mathematical expression or sometimes with the help of key. On the other hand decryption is the reverse process of encryption with help of same key used at encryption or with the help of some other key. The paper presents the different methodology used for encryption and decryption. Several methods presented in the literature are reviewed. The methods- Rivest-Shamir-Adlemen algorithm, Data Encryption Standard, Advanced Encryption Standard and three different Secure Hash Algorithm are reviewed and implemented using various FPGA devices. The power consumption, delay and area are analyzed and compared. From the analyses it is been found that the performance of AES and SHA3 are better when compared to other algorithms. These algorithms provide high security when compared to rest of the methods.

     

     

  • References

    1. [1] Amit T, Shriniwas D , Pritesh J & Akshay C, “Implementation of RSA Encryption Algorithm on FPGAâ€, American Journal of Engineering Research (AJER), Vol.4, No.6, (2015), pp.144-151.

      [2] Landge AR & Ansari AH, “RSA algorithm realization on FPGAâ€, International Journal of Advanced Research in Computer Engineering & Technology (IJARCET), Vol 2, No.7, (2013), pp.2323-2327.

      [3] Muhammad II, Mamun BIR, Khandaker A & Sazzad H, “FPGA Implementation of RSA Encryption Engine with Flexible Key Sizeâ€, International Journal of Communications, Vol.1, No.3, (2007), pp.107- 113.

      [4] Sushanta KS & Manoranjan P, “FPGA Implementation of RSA Encryption Systemâ€, International Journal of Computer Applications, Vol.19, No.9, (2011), pp.10-12.

      [5] Velibor S, Branko D & Zeljko I, “Hardware Modules of the RSA Algorithmâ€, Serbian Journal of Electrical Engineering, Vol.11, No.1, (2014), pp.121-131.

      [6] Rohith SP & Mahesh C, “FPGA Implementation of 16 bit RSA Cryptosystem for Text Messageâ€, International Journal of Computer Applications, Vol.92, No.8, (2014), pp.1-5.

      [7] Adriana NB, “Software Implementation of a Module for Encryption and Decryption Using the RSA Algorithmâ€, International Scientific Conference Electronics (ET), (2016), pp.1–4.

      [8] Sangita AJ & Santosh SC, “A Modified RSA Algorithm to Enhance Security for Digital Signatureâ€, International Conference and Workshop on Computing and Communication (IEMCON), (2015), pp.1-5.

      [9] Ji Y & Hongbo K, “FPGA Implementation of Dynamic Key Management for DES Encryption Algorithmâ€, International Conference on Electronic & Mechanical Engineering and Information Technology, (2011), pp.4795-4798.

      [10] Wuling R & Zhiqian M, “A Hybrid Encryption Algorithm Based on DES and RSA in Bluetooth Communicationâ€, Second International Conference on Modeling, Simulation and Visualization Methods, (2010), pp.221-225.

      [11] Jing W, Guo PJ & Hua Y, “Improved DES Algorithm based on Irrational Numbersâ€, IEEE Int. Conference Neural Networks & Signal Processing, (2008), pp.632–635.

      [12] Pradnya K & Phade GM, “Application of AES Algorithm for Data Security in Serial Communicationâ€, International Conference on Inventive Computation Technologies (ICICT), (2016), pp.1–5.

      [13] Guang LG, Quan Q & Rui Z, “Different Implementations of AES Cryptographic Algorithmâ€, IEEE 17th International Conference on High Performance Computing and Communications, (2015), pp.1848–1853.

      [14] Dilna V & Babu C, “Area Optimized and High Throughput AES Algorithm based on Permutation Data Scramble Approachâ€, International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), (2016), pp.3056–3060.

      [15] Savitha S & Yamuna S, “Implementation of AES Algorithm to Overt Fake Keys against Counter Attacksâ€, International Conference on Computer Communication and Informatics (ICCCI), (2016), pp.1-5.

      [16] Pritamkumar NK & Vrushali GR, “Implementation of AES Algorithm on FPGA for Low Area Consumptionâ€, International Conference on Pervasive Computing (ICPC), (2015), pp.1-4.

      [17] Senthil Kumar J & Mahalakshmi C, “Implementation of Pipelined Hardware Architecture for AES Algorithm using FPGAâ€, International Conference on Communication and Network Technologies (ICCNT), (2014), pp.260–264.

      [18] Nacci AA, Rana VSD & Santambrogio MD, “An open-source, efficient and parameterizable hardware implementation of the AES algorithmâ€, IEEE International Symposium on Parallel and Distributed Processing with Applications, (2014), pp.85-92.

      [19] Mazen EM, Salma H & Mohamed AAEG, “Real-Time Efficient FPGA Implementation of AES Algorithmâ€, IEEE International SOC Conference, (2013), pp.203–208.

      [20] Luminita S and Petre DM, “On the Substitution Method of the AES Algorithmâ€, International Symposium on Signals, Circuits and Systems (ISSCS), (2013), pp.1–4.

      [21] Kshirsagar RV & Vyawahare MV, “FPGA Implementation of High speed VLSI Architectures for AES Algorithmâ€, Fifth International Conference on Emerging Trends in Engineering and Technology, (2012), pp.239–242.

      [22] Junfeng C & Mohammed B, “Low Area Memory-Free FPGA Implementation of the AES Algorithmâ€, 22nd International Conference on Field Programmable Logic and Applications (FPL), (2012), pp.623–626.

      [23] Vanitha M & Sakthivel R, “Highly Secured High Throughput VLSI Architecture for AES Algorithmâ€, International Conference on Devices, Circuits and Systems (ICDCS), (2012), pp.403–407.

      [24] Atul MB, Kshirsagar RV & Vyawahare MV, “FPGA Implementation of AES Algorithmâ€, 3rd International Conference on Electronics Computer Technology, Vol.3, No.1, (2011), pp.401–405.

      [25] Magnus S & Ricardo C, “Efficient FPGA Implementation of the SHA-3 Hash Functionâ€, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), (2017), pp.86–91.

      [26] Muhammad A, Muhammad A, Nasir M & Arshad A, “Compact Hardware Implementation of SHA-3 Finalist Blake on FPGAâ€, IEEE 9th International Conference on Emerging Technologies (ICET), (2013), pp.1–5.

      [27] Fatma K, Belgacem B, Mohsen M & Rached T, “An FPGA implementation of the SHA-3: The BLAKE Hash Functionâ€, International Multi-Conferences on Systems, Signals & Devices (SSD13), (2013), pp.1–5.

      [28] Kuntoro A, Arimaz H & Made S, “SHA-2 and SHA-3 Based Sequence Randomization Algorithmâ€, 2nd International Conference on Science and Technology-Computer (ICST), (2016), pp.150–154.

      [29] Kazuyuki K, Jun I, Miroslav K & Eric XG, “Prototyping Platform for Performance Evaluation of SHA-3 Candidatesâ€, IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), (2010), pp.60–63.

      [30] Jens-Peter K, Panasayya Y, Kishore KS, Bilal H, Susheel V & Smriti G, “Lightweight Implementations of SHA-3 Finalists on FPGAsâ€, International Conference on Cryptology, (2011), pp.270-289.

      [31] Bernhard J & Jurgen A, “Area-efficient FPGA Implementations of the SHA-3 Finalistsâ€, International Conference on Reconfigurable Computing and FPGAs, (2011), pp.235–241.

      [32] Yusuke A, Naoki F & Shuichi I, “Design Trade-offs in SHA-3 multi-message hashing on FPGAsâ€, TENCON 2014-2014 IEEE Region 10 Conference, (2014), pp.1-5.

      [33] Bernhard J & Marc S, “Hobbit - Smaller But Faster Than A Dwarf: Revisiting Lightweight SHA-3 FPGA Implementationsâ€, International Conference on Reconfigurable Computing and FPGAs (ReConFig), (2016), pp.1-7.

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  • How to Cite

    Neelima, S., & Brinda, R. (2018). Implementation of various data encryption methods for medical information transmission. International Journal of Engineering & Technology, 7(2.31), 219-224. https://doi.org/10.14419/ijet.v7i2.31.13446

    Received date: 2018-05-29

    Accepted date: 2018-05-29

    Published date: 2018-05-29