FPGA implementation of 1000base-x Ethernet physical layer core

  • Authors

    • Eman Salem benha university
    • Abdelhalim Zekry Ain Shams University
    • Hossam Labeb benha university
    • Radwa Tawfik benha university
    2018-09-10
    https://doi.org/10.14419/ijet.v7i4.13469
  • Giga Ethernet, virtex6 FPGA, PHY, PCS, PMA, 8B/10B Coding, Synchronization, PISO, SIPO.

  • Abstract

    This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.

     

     

  • References

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  • How to Cite

    Salem, E., Zekry, A., Labeb, H., & Tawfik, R. (2018). FPGA implementation of 1000base-x Ethernet physical layer core. International Journal of Engineering & Technology, 7(4), 2106-2112. https://doi.org/10.14419/ijet.v7i4.13469

    Received date: 2018-05-29

    Accepted date: 2018-08-25

    Published date: 2018-09-10