Low leakage SRAM cell for ULP applications

  • Authors

    • Tripti Tripathi IPEC
    • D. S. Chauhan GLA University
    • S. K. Singh ABES Engineering College
    2018-09-24
    https://doi.org/10.14419/ijet.v7i4.14028
  • SRAM, Low Power, Leakage Current, Fingering, CMOS.

  • Abstract

    Leakage power is becoming a major concern in battery operated and hand held devices. With the ever reducing size of electronic devices and the use of memory in most of them, the need for low power devices is vastly increasing. These devices are either in active or standby mode of operation. Leakage power in standby mode of operation is of major concern and various methods to minimize it have been proposed at various stages of design cycle. This paper proposes fingering technique that can be used in 6T SRAM cell to reduce leakage power. Leakage power is calculated for 6T SRAM cell designed using two fingers in access transistors and on comparison with conventional 6T SRAM cell, significant reduction in leakage current is obtained. The layout has been designed in UMC 55nm technology using Cadence Virtuoso tool and it has been shown that the leakage power and delay can be reduced.

     

     

  • References

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  • How to Cite

    Tripathi, T., S. Chauhan, D., & K. Singh, S. (2018). Low leakage SRAM cell for ULP applications. International Journal of Engineering & Technology, 7(4), 2521-2524. https://doi.org/10.14419/ijet.v7i4.14028

    Received date: 2018-06-11

    Accepted date: 2018-08-18

    Published date: 2018-09-24