High performance turbo encoder using mealy FSM state encoding technique

  • Authors

    • E Sujatha
    • Dr C. Subhas
    • Dr M. N. Giri Prasad
    2018-06-08
    https://doi.org/10.14419/ijet.v7i2.33.14163
  • LTE-A Standard, Turbo Encoder, QPP Interleaver, FSM Technique, Look Up Table (LUT), Parallel Architecture.

  • Abstract

    Error-correction Coding plays a vital role to obtain efficient and high quality data transmission, in today’s high speed wireless communication system. Considering the requirement of using high data rates by Long Term Evolution (LTE) system, parallel concatenation of two convolutional encoders were used to design turbo encoder. In this research task a high speed turbo encoder, which is a key component in the transmitter of wireless communication System, with memory based interleaver has been designed and implemented on FPGA for 3rd Generation Partnership Project (3GPP) defined Long Term Evolution – Advanced (LTE-A) standard using Finite state Machine(FSM) encoding technique. Memory based quadratic permutation polynomial (QPP) interleaver shuffles a sequence of binary data and supports any of the 188 block sizes from N= 40 to N= 6144. The proposed turbo encoder is implemented using 28nm CMOS technology and achieved 300 Mbps data rate by using 1% of available total hardware logic. By using the proposed technique, encoded data can be released continuously with the help of two parallel memories to write/read the input using pipelining concept.

     

     

  • References

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  • How to Cite

    Sujatha, E., C. Subhas, D., & M. N. Giri Prasad, D. (2018). High performance turbo encoder using mealy FSM state encoding technique. International Journal of Engineering & Technology, 7(2.33), 255-258. https://doi.org/10.14419/ijet.v7i2.33.14163

    Received date: 2018-06-17

    Accepted date: 2018-06-17

    Published date: 2018-06-08