Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)

  • Authors

    • P Sasipriya VIT, Chennai
    • V S Kanchana Bhaaskaran VIT, Chennai
    2018-07-19
    https://doi.org/10.14419/ijet.v7i3.14632
  • Low Power, Quasi-Adiabatic Logic, Two Phase Clocked Charge Recovery Circuit, Low Power Adder

  • Abstract

    This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate
    efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.

     

     

  • References

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  • How to Cite

    Sasipriya, P., & S Kanchana Bhaaskaran, V. (2018). Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL). International Journal of Engineering & Technology, 7(3), 1548-1551. https://doi.org/10.14419/ijet.v7i3.14632

    Received date: 2018-06-23

    Accepted date: 2018-07-06

    Published date: 2018-07-19