Design of Low Delay Ring Oscillator Using CMOS

  • Authors

    • S Shiyamala
    • T Kavitha
    2018-07-04
    https://doi.org/10.14419/ijet.v7i3.6.15126
  • Ring oscillator, transistor size, delay, chain stage.

  • Abstract

    In the Era of digital World, low power applications are the needs of the market to save the resources. Delay elements (e.g. digital clock) are essential parts of such digital applications. Ring oscillators have been used because of their ease of implementation, wide tuning ranges, operating at low voltages and existing possibility of complete integration in standard CMOS processes. It desires at identifying the best possible configuration for the hoop oscillators having the least strength intake and precise delay with lesser sensitivity to the variations inside the temperature and deliver voltage for frequencies of few KHz. while N = 7, for  0.18 µm generation , put off is 0.07ns simplest. Compare with N = 3, 14.2 % delay time reduced and 12.6 % lower when N= 7 taken into account.

     

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  • How to Cite

    Shiyamala, S., & Kavitha, T. (2018). Design of Low Delay Ring Oscillator Using CMOS. International Journal of Engineering & Technology, 7(3.6), 334-336. https://doi.org/10.14419/ijet.v7i3.6.15126

    Received date: 2018-07-05

    Accepted date: 2018-07-05

    Published date: 2018-07-04