Design of ASIC Square Calculator Using AncientVedic Mathematics

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.

     

     


  • Keywords


    Multiplier; Square calculator; Urdhva Tiryagbyham; Vedic mathematics.

  • References


      [1] K. K. Parhi (1999) “VLSI digital processing systems: design and implementation,” Willy-India, ISBN: 978-0-471-24186-7.

      [2] Harpreet Singh Dhillon & Abhijit Mitra (2008) “A Reduced-Bit Multiplication Algorithm for Digital Arithmetic,” World Academy of Science, Engineering and Technology, International Journal of Electronics and Communication Engineering, Vol. 2, No. 7, pp. 650-655.

      [3] C. Sheshavali & K. Niranjan Kumar (2013) “Design and implementation of vedic multiplier,” International Journal of Engineering Research and Development, Vol. 8, Issue-6, pp. 23-28, e-ISSN: 2278-067X, p-ISSN: 2278-800X.

      [4] P. Saha, Deepak Kumar, Partha Bhattacharyya & Anup Dandapat (2014) “Design of 64-bit squarer based on vedic mathematics,” Journal of Circuits, Systems, and Computers, Vol. 23, No. 7, p. 1450092-16, DOI: https://doi.org/10.1142/S0218126614500923.

      [5] A. D. Booth (1951) “A signed binary multiplication technique,” Quarterly Journal of Mechanics and Applied Mathematics, Vol. 4, Issue-2, pp. 236–240, DOI: https://doi.org/10.1093/qjmam/4.2.236.

      [6] P. Saha, A. Banerjee, A. Dandapat, P. Bhattacharyya (2011 ) “Vedic mathematics based 32-bit multiplier design for high speed low power processor”, International Journal On Smart Sensing And Intelligent Systems, Vol. 4, No. 2, pp. 268-284, ISSN: 1178-5608.

      [7] Jagadguru Swami Sri Bharath, Krsna Tirathji, (1990) “Vedic mathematics or sixteen simple sutras from the vedas”, Motilal Banarsidas Publishers, Varanasi (India), ISBN: 8120801636.

      [8] Himansh Thapliyal & M.B. Srinivas (2004) “High speed efficient N X N nit parallel hierarchical overlay multiplier architecture based on ancient indian vedic mathematics,” Transactions on Engineering, Computing And Technology V2, pp.225-228, ISSN:1305-5313.

      [9] Pushpalata Verma (2012) “Design of 4x4 bit vedic multiplier using EDA tool”, International Journal of Computer Applications (0975 – 888), Vol. 48, No. 20, pp.32-35.

      [10] R. Sridevi, Anirudh Palakurthi, Akhila Sadhula & Hafsa Mahreen (2013) “Design of a high speed multiplier (ancient vedic mathematics approach)”, International Journal of Engineering Research, Vol.-2, Issue-3, pp. 183-186, ISSN: 2319-6890.

      [11] P. Meheta & D. Gawali (2009) “Conventional versus vedic mathematical method for hardwared implitation of a multiplier”, Proceedings of IEEE International conferences on Advances in computing, control and telecommunication, Trivandam, Kerela, pp. 640-642, DOI: 10.1109/ACT.2009.162.

      [12] G. G. Kumar & V. Charishma (2013) “Design of high speed vedic multiplier using vedic mathematics technology”, IJSR publications, Vol. 2, Issue-3, March, pp.1-5, ISSN: 2250-3153.

      [13] P. Saha, A. Banerjee, A. Dandapat & P. Bhattacharyya (2011) “ASIC design of a high speed low power circuit for factorial calculation using ancient vedic mathematics,” Microelectronics Journal, Vol. 42, Issue-12, pp. 1343-1352, DOI: 10.1016/j.mejo.2011.09.001.

      [14] Prabir Saha, Arindam Banerjee, Partha Bhattacharyya & Anup Dandapat (2014) “Improved matrix multiplier design for high speed signal processing applications,” IET circuits, devices & systems, Vol. 8, Issue-1, pp.27-37, DOI: 10.1049/iet-cds.2013.0117.

      [15] Angshuman Khan & Rupayan Das (2015) “Novel Approach of Multiplier Design using ancient Vedic Mathematics,” Springer series of Advances in Intelligent Systems and Computing (AISC), Vol-340, pp.265-272, DOI: 10.1007/978-81-322-2247-7_28.

      [16] Angshuman Khan, Souvik Saha, Asmita Chakraborty & Rupayan Das (2015) “Digital Multiplier to Multiply Special Integers using ancient Vedic Mathematics,” International Conference on Inter Disciplinary Research in Engineering and Technology, pp. 209-213, ISBN: 978-81-929742-5-5.

      [17] A. Khan et al. (2017) “Robust high speed ASIC design of a vedic square calculator using ancient Vedic mathematics,” 8th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), Vancouver, BC, pp. 710-713, DOI: 10.1109/IEMCON.2017.8117240.


 

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Article ID: 15334
 
DOI: 10.14419/ijet.v7i2.23.15334




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