Design of ASIC Square Calculator Using AncientVedic Mathematics

  • Authors

    • Angshuman Khan
    • Sudip Halder
    • Shubhajit Pal
    2018-04-20
    https://doi.org/10.14419/ijet.v7i2.23.15334
  • Multiplier, Square calculator, Urdhva Tiryagbyham, Vedic mathematics.

  • Abstract

    This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.

     

     

  • References

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  • How to Cite

    Khan, A., Halder, S., & Pal, S. (2018). Design of ASIC Square Calculator Using AncientVedic Mathematics. International Journal of Engineering & Technology, 7(2.23), 464-466. https://doi.org/10.14419/ijet.v7i2.23.15334

    Received date: 2018-07-09

    Accepted date: 2018-07-09

    Published date: 2018-04-20