Design of ALU System Using Novel PMOS and NMOS for Low Power and High Speed Applications

  • Authors

    • Ashok Babu CH
    • J V.R. Ravindra
    • K Lalkishore
    2018-04-20
    https://doi.org/10.14419/ijet.v7i2.23.15343
  • conventional NMOS, conventional PMOS, high speed, novel NMOS, novel PMOS, power delay product.

  • This paper tailors 8 bit ALU for high speed and low power applications. In this design a novel PMOS and NMOS are used in place of conventional PMOS and NMOS. The main disadvantage of conventional PMOS and NMOS is low speed. With the technique of forward body biasing a novel PMOS and NMOS are derived and speed is improved. For each sub module of ALU power delay product percentage is calculated. Percentage improvement in power delay product of Novel ALU is shown in table 27.

     

     

  • References

    1. [1] Ahmed Chefi, Adel Soudani, Gilles Sicard, “Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs†AEU - International Journal of Electronics and Communications, Volume 68, Issue 3, March 2014, Pages 193-200.

      [2] Sayed Rasoul Faraji, Amin Salari, Samad Sheikhaei, “Fixed-point implementation of interpolation-based MMSE MIMO detector in joint transmission scenario for LTE-A wireless standardâ€, AEU - International Journal of Electronics and Communications, Volume 70, Issue 11, November 2016, Pages 1506-1514.

      [3] Naser Beyraghi, Abdollah Khoei, “CMOS design of a low power and high precision four-quadrant analog multiplierâ€, AEU - International Journal of Electronics and Communications, Volume 69, Issue 1, January 2015, Pages 400-407.

      [4] Suma T.Hegde, Dr. Siva Yellampalli and Nandeesh R, “Design and Implementation of ALU using Redundant Binary Signed Digitâ€, International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011, Proceedings published by International Journal of Computer Applications® (IJCA), pp: 30-35.

      [5] Mahendra Kumar and Kailash Chandra “Low Power High Performance SRAM Design Using VHDLâ€, Global Journal of Researches in Engineering, Volume 11 Issue 1 Version 1.0 February, 2011, ISSN: 0975-5861, pp: 21- 24.

      [6] H.T. Bui, Y. Wang and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gatesâ€, IEEE Trans. On Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, pp. 25 –30, Jan. 2002.

      [7] J.M. Wang, S.C. Fang and W.C. Fang, “New efficient designs for XOR and XNOR functions on transistor levelâ€, IEEE J. of Solid State Circuits, vol. 29, pp. 780-786, July 1994.

      [8] A.M. Shams and M.A. Bayoumi, “A novel high-performance CMOS 1-bit full-adder cellâ€, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 478 –481, May 2000. 105.

      [9] D. Radhakrishnan, “Low-voltage low-power CMOS full adderâ€, IEE Proceedings-Circuits, Devices and Systems, vol.148, pp. 19 - 24, Feb. 2001.

      [10] Arvind Rajput, Anil Goyal, “DESIGN AND COMPARISON OF LOW POWER & HIGH SPEED 4-BIT ALUâ€, Proc. of 2nd National Conference on Challenges & Opportunities in Information Technology (COIT-2008), RIMT-IET, Mandi Gobindgarh. March 29, 2008.

      [11] A. Srivastava and C. Srinivasan, “ ALU Design using Reconfigurable CMOS Logicâ€, Proc. of the 45th IEEE 2002 Midwest Symposium on Circuits and Systems, vol.2, pp. 663-666, Aug. 2002.

      [12] V.G. Mobdzija, “A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approachâ€, IEEE Transactions on Computers, vol. 45, No, 3, pp. 294-305,1996.

      [13] A. Kamaraj , I. Vivek Anand and P. Marichamy ‘’ Design of Low Power Combinational Circuits Using Reversible Logic and Realization in Quantum Cellular Automata’’.IEEE International Conference on Innovations in Engineering andTechnology (ICIET’14) Volume 3, Special Issue 3, March 2014.

      [14] Akash Goel,Vineet Monga, Manish Bhalla,Arti Saxena ’’ Half Adder, Half Subtractor and Full Adder by Using Reversible Gates’’. National Student Conference On “Advances in Electrical & Information Communication Technologyâ€AEICT- 2014.

      [15] Akanksha Dixit, Vinod Kapse, “Arithmetic & Logic Unit (ALU) Design using Reversible Control Unit†International Journal of Engineering and Innovative Technology (IJEIT) Volume 1, Issue 6, June 2012.

      [16] G.V.V.S.R. Krishna †Behavioral Analysis of Different ALU Architectures†International Journal of Electronics and Computer Science Engineering, 2277-1956/V1N3-1482-1488.

      [17] B. Lokesh , K. Dushyanth “ 4 -Bit Reconfigurable ALU with Minimum Power and Delay†International Journal of Computer Applications.

      [18] P. Chandrakasan, S.Sheng, and R.W.Broderson, “Low-power CMOS digital design,†IEEE J. Solid-State Circuits, vol. 27, pp. 473–483, Apr. 1992.

      [19] R.Zimmermannn and W.Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,†IEEE J. SolidState Circuits, vol. 32, pp. 1079–1090, July 1997.

      [20] Guang-Ming Tang; Kensuke Takata; Masamitsu Tanaka; Akira Fujimaki; Kazuyoshi Takagi; Naofumi Takagi, “4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessorsâ€, IEEE Transactions on Applied Superconductivity Year: 2016, Volume: 26, Issue: 1.

      [21] Kanimozhi V.; Gowri Shankar R., “Design and implementation of Arithmetic Logic Unit (ALU) using modified novel bit adder in QCAâ€, 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS).

      [22] Nidhi Gupta, “Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGAâ€, 2014 International Conference on Computational Intelligence and Communication Networks.

  • Downloads

  • How to Cite

    Babu CH, A., V.R. Ravindra, J., & Lalkishore, K. (2018). Design of ALU System Using Novel PMOS and NMOS for Low Power and High Speed Applications. International Journal of Engineering & Technology, 7(2.23), 498-504. https://doi.org/10.14419/ijet.v7i2.23.15343