An area efficient approach on nonvolatile processors using pack architecture

Abstract

Nonvolatile processor can hold its state when the power is off. The major drawback of the nonvolatile processor is the excess area occupied by the nonvolatile registers in it. Contrasted with consistent CMOS flip-flop, the ferro electric nonvolatile flip-flop takes a vast area because of its hybrid structure. Later nonvolatile processor with floating gate transistor was developed. But this structure also has a drawback that it occupies 40% of memory area. In this paper, Parallel Compare and Compress (PaCC) design architecture is utilized to reduce the area of the nonvolatile registers in the non-volatile processors. The fundamental blocks in PaCC design are PaCC encoder, PaCC decoder, volatile registers, nonvolatile registers and nonvolatile flip flop controllers. The PaCC encoder and the PaCC decoder are the works that are mainly focused in this paper. The PaCC design utilizes Run length encoder (RLE) technique. Run length encoder (RLE) is a simple technique used for compressing data. Here runs of data’s are stored as a single data value and as count. The PaCC decoder decodes the outputs from the PaCC encoder, thus the original input data can be obtained. The results shows that this design architecture can reduce the number of nonvolatile registers by 70%-80%, thereby reducing the overall area. The design was modeled using VHDL in Xilinx ISE Design Suite 14.5 and simulated using Modelsim 6.5b.