Low power multiply accumulate unit based on modified hybrid Han Carlson adder

  • Authors

    • Rakesh S NOORUL ISLAM CENTRE FOR HIGHER EDUCATION
    • K. S. Vijula Grace NOORUL ISLAM CENTRE FOR HIGHER EDUCATION
    2019-01-22
    https://doi.org/10.14419/ijet.v8i1.1.15803
  • Digital Signal Processor, Field Programmable Gate Array, Hybrid Han Carlson Adder, Modified Inequality Detector, Multiply Accumulate Unit.

  • Abstract

    The aim of this work is to propose a modified architecture for implementing Multiply Accumulate (MAC) unit which can be used to build a low power Digital Signal Processor (DSP). The method improves the power consumption as well as the power-delay product. The proposed method uses hybrid parallel prefix adder in the multiplier stage and in the adder stage. In the architecture, a Hybrid Han      Carlson adder with modified pre-processing and post-processing stages (HHCA_MPPS) is used. The units are designed using Verilog Hardware Description Language (HDL) and simulated and synthesized for Artix-7 series Field Programmable Gate Array (FPGA) using Xilinx Vivado Design Suite 2015.2. The analysis showed that the proposed design has significant improvement in the power              consumption and the figure of merit (power-delay product). The MAC unit employing modified hybrid Han Carlson adder gave a power saving of 11.57% and improvement of 9.21% in the power-delay product.

     

  • References

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  • How to Cite

    S, R., & S. Vijula Grace, K. (2019). Low power multiply accumulate unit based on modified hybrid Han Carlson adder. International Journal of Engineering & Technology, 8(1), 1-7. https://doi.org/10.14419/ijet.v8i1.1.15803

    Received date: 2018-07-18

    Accepted date: 2019-01-03

    Published date: 2019-01-22