FPGA Implementation of UART with Single Error Correction and Double Error Detection (UART-SEC-DED)

  • Authors

    • Amrutha Gorabal
    • Nayana D K
    2018-07-20
    https://doi.org/10.14419/ijet.v7i3.12.15856
  • AES, ASIC, Data security, GPP, VLIW architecture.

  • Abstract

    The Universal Asynchronous Receiver Transmitter (UART) is the very simple and significant sequential communication protocol which is basically utilized for microprocessors & microcontroller systems. It is a shorter range communication protocol, which able to perform half-duplex and full-duplex type of communication at baud rates. Though, UART is a type of shorter range communication still they are not resistant to noisy channel which leads to communication errors by flipping or loosing of bits. These kinds of signal errors are named as forward-errors. The correction of forward errors is a mechanism to handle and rectify those errors (i.e. Burst errors and Random bits error). Thus in this methodology, have introduced a UART-SEC-DED communication module design which utilizes the Hamming encoder and decoders to achieve the forward error correction. Finally, the proposed system will simulated and implemented on FPGA board and experimental outcomes shows the better efficiency in single error correction and detection of double errors.

     

     

  • References

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  • How to Cite

    Gorabal, A., & D K, N. (2018). FPGA Implementation of UART with Single Error Correction and Double Error Detection (UART-SEC-DED). International Journal of Engineering & Technology, 7(3.12), 23-27. https://doi.org/10.14419/ijet.v7i3.12.15856

    Received date: 2018-07-19

    Accepted date: 2018-07-19

    Published date: 2018-07-20