Controlling of PV-STATCOM for Increasing Power Transmission based on VHDL Signal Generation

Abstract

Along with Generation of power, distribution of power is equally important.The power produced by the solar farm are utilized only during daytime, the solar farm remain idle during night and operate below capacity in initial morning and late afternoon. A grid connected solar farm uses photovoltaic (PV) arrays for generation of DC power which is transformed to AC using inverter modeling. A FACTS family device STATCOM is centered on a voltage source converter which operates as a rectifier and an inverter is used to enhance steady power transmission limits with reactive power, voltage and damping control. A majorsection of the STATCOM is a voltage source converter which is also anessential element of PV solar module. A novel concept was proposed by which PV solar module can be operated as a STATCOM, known as PV-STATCOM in the night-time and day time. VLSI technology is used to generate the trigger pulses for three phase inverter using the VHDL programming language to generate the signal for the control of inverter section in STATCOM. The HDL compiling and FPGA implementation is done using MATLAB/SIMULINK.